Bug Summary

File:hw/arm/highbank.c
Location:line 292, column 9
Description:Function call argument is an uninitialized value

Annotated Source Code

1/*
2 * Calxeda Highbank SoC emulation
3 *
4 * Copyright (c) 2010-2012 Calxeda
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 */
19
20#include "hw/sysbus.h"
21#include "hw/arm/arm.h"
22#include "hw/devices.h"
23#include "hw/loader.h"
24#include "net/net.h"
25#include "sysemu/sysemu.h"
26#include "hw/boards.h"
27#include "sysemu/blockdev.h"
28#include "exec/address-spaces.h"
29#include "qemu/error-report.h"
30
31#define SMP_BOOT_ADDR0x100 0x100
32#define SMP_BOOT_REG0x40 0x40
33#define MPCORE_PERIPHBASE0xfff10000 0xfff10000
34
35#define NIRQ_GIC160 160
36
37/* Board init. */
38
39static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
40{
41 int n;
42 uint32_t smpboot[] = {
43 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
44 0xe210000f, /* ands r0, r0, #0x0f */
45 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
46 0xe0830200, /* add r0, r3, r0, lsl #4 */
47 0xe59f2024, /* ldr r2, privbase */
48 0xe3a01001, /* mov r1, #1 */
49 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
50 0xe3a010ff, /* mov r1, #0xff */
51 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
52 0xf57ff04f, /* dsb */
53 0xe320f003, /* wfi */
54 0xe5901000, /* ldr r1, [r0] */
55 0xe1110001, /* tst r1, r1 */
56 0x0afffffb, /* beq <wfi> */
57 0xe12fff11, /* bx r1 */
58 MPCORE_PERIPHBASE0xfff10000 /* privbase: MPCore peripheral base address. */
59 };
60 for (n = 0; n < ARRAY_SIZE(smpboot)(sizeof(smpboot) / sizeof((smpboot)[0])); n++) {
61 smpboot[n] = tswap32(smpboot[n]);
62 }
63 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR)rom_add_blob("smpboot", smpboot, sizeof(smpboot), 0x100, ((void
*)0), ((void*)0), ((void*)0));
64}
65
66static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
67{
68 CPUARMState *env = &cpu->env;
69
70 switch (info->nb_cpus) {
71 case 4:
72 stl_phys_notdirty(SMP_BOOT_REG0x40 + 0x30, 0);
73 case 3:
74 stl_phys_notdirty(SMP_BOOT_REG0x40 + 0x20, 0);
75 case 2:
76 stl_phys_notdirty(SMP_BOOT_REG0x40 + 0x10, 0);
77 env->regs[15] = SMP_BOOT_ADDR0x100;
78 break;
79 default:
80 break;
81 }
82}
83
84#define NUM_REGS0x200 0x200
85static void hb_regs_write(void *opaque, hwaddr offset,
86 uint64_t value, unsigned size)
87{
88 uint32_t *regs = opaque;
89
90 if (offset == 0xf00) {
91 if (value == 1 || value == 2) {
92 qemu_system_reset_request();
93 } else if (value == 3) {
94 qemu_system_shutdown_request();
95 }
96 }
97
98 regs[offset/4] = value;
99}
100
101static uint64_t hb_regs_read(void *opaque, hwaddr offset,
102 unsigned size)
103{
104 uint32_t *regs = opaque;
105 uint32_t value = regs[offset/4];
106
107 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
108 value |= 0x30000000;
109 }
110
111 return value;
112}
113
114static const MemoryRegionOps hb_mem_ops = {
115 .read = hb_regs_read,
116 .write = hb_regs_write,
117 .endianness = DEVICE_NATIVE_ENDIAN,
118};
119
120#define TYPE_HIGHBANK_REGISTERS"highbank-regs" "highbank-regs"
121#define HIGHBANK_REGISTERS(obj)((HighbankRegsState *)object_dynamic_cast_assert(((Object *)(
(obj))), ("highbank-regs"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 121, __func__)) \
122 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)((HighbankRegsState *)object_dynamic_cast_assert(((Object *)(
(obj))), ("highbank-regs"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 122, __func__))
123
124typedef struct {
125 /*< private >*/
126 SysBusDevice parent_obj;
127 /*< public >*/
128
129 MemoryRegion iomem;
130 uint32_t regs[NUM_REGS0x200];
131} HighbankRegsState;
132
133static VMStateDescription vmstate_highbank_regs = {
134 .name = "highbank-regs",
135 .version_id = 0,
136 .minimum_version_id = 0,
137 .minimum_version_id_old = 0,
138 .fields = (VMStateField[]) {
139 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS){ .name = ("regs"), .version_id = (0), .num = (0x200), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(HighbankRegsState
, regs) + ((uint32_t(*)[0x200])0 - (typeof(((HighbankRegsState
*)0)->regs)*)0)), },
140 VMSTATE_END_OF_LIST(){},
141 },
142};
143
144static void highbank_regs_reset(DeviceState *dev)
145{
146 HighbankRegsState *s = HIGHBANK_REGISTERS(dev)((HighbankRegsState *)object_dynamic_cast_assert(((Object *)(
(dev))), ("highbank-regs"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 146, __func__));
147
148 s->regs[0x40] = 0x05F20121;
149 s->regs[0x41] = 0x2;
150 s->regs[0x42] = 0x05F30121;
151 s->regs[0x43] = 0x05F40121;
152}
153
154static int highbank_regs_init(SysBusDevice *dev)
155{
156 HighbankRegsState *s = HIGHBANK_REGISTERS(dev)((HighbankRegsState *)object_dynamic_cast_assert(((Object *)(
(dev))), ("highbank-regs"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 156, __func__));
157
158 memory_region_init_io(&s->iomem, OBJECT(s)((Object *)(s)), &hb_mem_ops, s->regs,
159 "highbank_regs", 0x1000);
160 sysbus_init_mmio(dev, &s->iomem);
161
162 return 0;
163}
164
165static void highbank_regs_class_init(ObjectClass *klass, void *data)
166{
167 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass)((SysBusDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 167, __func__));
168 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 168, __func__));
169
170 sbc->init = highbank_regs_init;
171 dc->desc = "Calxeda Highbank registers";
172 dc->vmsd = &vmstate_highbank_regs;
173 dc->reset = highbank_regs_reset;
174}
175
176static const TypeInfo highbank_regs_info = {
177 .name = TYPE_HIGHBANK_REGISTERS"highbank-regs",
178 .parent = TYPE_SYS_BUS_DEVICE"sys-bus-device",
179 .instance_size = sizeof(HighbankRegsState),
180 .class_init = highbank_regs_class_init,
181};
182
183static void highbank_regs_register_types(void)
184{
185 type_register_static(&highbank_regs_info);
186}
187
188type_init(highbank_regs_register_types)static void __attribute__((constructor)) do_qemu_init_highbank_regs_register_types
(void) { register_module_init(highbank_regs_register_types, MODULE_INIT_QOM
); }
189
190static struct arm_boot_info highbank_binfo;
191
192enum cxmachines {
193 CALXEDA_HIGHBANK,
194 CALXEDA_MIDWAY,
195};
196
197/* ram_size must be set to match the upper bound of memory in the
198 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
199 * normally 0xff900000 or -m 4089. When running this board on a
200 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
201 * device tree and pass -m 2047 to QEMU.
202 */
203static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
204{
205 ram_addr_t ram_size = args->ram_size;
206 const char *cpu_model = args->cpu_model;
207 const char *kernel_filename = args->kernel_filename;
208 const char *kernel_cmdline = args->kernel_cmdline;
209 const char *initrd_filename = args->initrd_filename;
210 DeviceState *dev = NULL((void*)0);
211 SysBusDevice *busdev;
212 qemu_irq pic[128];
213 int n;
214 qemu_irq cpu_irq[4];
215 MemoryRegion *sysram;
216 MemoryRegion *dram;
217 MemoryRegion *sysmem;
218 char *sysboot_filename;
219
220 if (!cpu_model) {
2
←
Assuming 'cpu_model' is non-null
→
3
←
Taking false branch
→
221 switch (machine) {
222 case CALXEDA_HIGHBANK:
223 cpu_model = "cortex-a9";
224 break;
225 case CALXEDA_MIDWAY:
226 cpu_model = "cortex-a15";
227 break;
228 }
229 }
230
231 for (n = 0; n < smp_cpus; n++) {
4
←
Assuming 'n' is >= 'smp_cpus'
→
5
←
Loop condition is false. Execution continues on line 252
→
232 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU"arm-cpu", cpu_model);
233 ARMCPU *cpu;
234 Error *err = NULL((void*)0);
235
236 cpu = ARM_CPU(object_new(object_class_get_name(oc)))((ARMCPU *)object_dynamic_cast_assert(((Object *)((object_new
(object_class_get_name(oc))))), ("arm-cpu"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 236, __func__));
237
238 object_property_set_int(OBJECT(cpu)((Object *)(cpu)), MPCORE_PERIPHBASE0xfff10000, "reset-cbar",
239 &err);
240 if (err) {
241 error_report("%s", error_get_pretty(err));
242 exit(1);
243 }
244 object_property_set_bool(OBJECT(cpu)((Object *)(cpu)), true1, "realized", &err);
245 if (err) {
246 error_report("%s", error_get_pretty(err));
247 exit(1);
248 }
249 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu)((DeviceState *)object_dynamic_cast_assert(((Object *)((cpu))
), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 249, __func__)), ARM_CPU_IRQ0);
250 }
251
252 sysmem = get_system_memory();
253 dram = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
254 memory_region_init_ram(dram, NULL((void*)0), "highbank.dram", ram_size);
255 /* SDRAM at address zero. */
256 memory_region_add_subregion(sysmem, 0, dram);
257
258 sysram = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
259 memory_region_init_ram(sysram, NULL((void*)0), "highbank.sysram", 0x8000);
260 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
261 if (bios_name != NULL((void*)0)) {
6
←
Assuming 'bios_name' is equal to null
→
7
←
Taking false branch
→
262 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS0, bios_name);
263 if (sysboot_filename != NULL((void*)0)) {
264 uint32_t filesize = get_image_size(sysboot_filename);
265 if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
266 hw_error("Unable to load %s\n", bios_name);
267 }
268 } else {
269 hw_error("Unable to find %s\n", bios_name);
270 }
271 }
272
273 switch (machine) {
8
←
Control jumps to 'case CALXEDA_MIDWAY:' at line 282
→
274 case CALXEDA_HIGHBANK:
275 dev = qdev_create(NULL((void*)0), "l2x0");
276 qdev_init_nofail(dev);
277 busdev = SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 277, __func__));
278 sysbus_mmio_map(busdev, 0, 0xfff12000);
279
280 dev = qdev_create(NULL((void*)0), "a9mpcore_priv");
281 break;
282 case CALXEDA_MIDWAY:
283 dev = qdev_create(NULL((void*)0), "a15mpcore_priv");
284 break;
9
←
 Execution continues on line 286
→
285 }
286 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
287 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC160);
288 qdev_init_nofail(dev);
289 busdev = SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 289, __func__));
290 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE0xfff10000);
291 for (n = 0; n < smp_cpus; n++) {
10
←
Assuming 'n' is < 'smp_cpus'
→
11
←
Loop condition is true. Entering loop body
→
292 sysbus_connect_irq(busdev, n, cpu_irq[n]);
12
←
Function call argument is an uninitialized value
293 }
294
295 for (n = 0; n < 128; n++) {
296 pic[n] = qdev_get_gpio_in(dev, n);
297 }
298
299 dev = qdev_create(NULL((void*)0), "sp804");
300 qdev_prop_set_uint32(dev, "freq0", 150000000);
301 qdev_prop_set_uint32(dev, "freq1", 150000000);
302 qdev_init_nofail(dev);
303 busdev = SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 303, __func__));
304 sysbus_mmio_map(busdev, 0, 0xfff34000);
305 sysbus_connect_irq(busdev, 0, pic[18]);
306 sysbus_create_simple("pl011", 0xfff36000, pic[20]);
307
308 dev = qdev_create(NULL((void*)0), "highbank-regs");
309 qdev_init_nofail(dev);
310 busdev = SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 310, __func__));
311 sysbus_mmio_map(busdev, 0, 0xfff3c000);
312
313 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
314 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
315 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
316 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
317 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
318 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
319
320 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
321
322 if (nd_table[0].used) {
323 qemu_check_nic_model(&nd_table[0], "xgmac");
324 dev = qdev_create(NULL((void*)0), "xgmac");
325 qdev_set_nic_properties(dev, &nd_table[0]);
326 qdev_init_nofail(dev);
327 sysbus_mmio_map(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 327, __func__)), 0, 0xfff50000);
328 sysbus_connect_irq(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 328, __func__)), 0, pic[77]);
329 sysbus_connect_irq(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 329, __func__)), 1, pic[78]);
330 sysbus_connect_irq(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 330, __func__)), 2, pic[79]);
331
332 qemu_check_nic_model(&nd_table[1], "xgmac");
333 dev = qdev_create(NULL((void*)0), "xgmac");
334 qdev_set_nic_properties(dev, &nd_table[1]);
335 qdev_init_nofail(dev);
336 sysbus_mmio_map(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 336, __func__)), 0, 0xfff51000);
337 sysbus_connect_irq(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 337, __func__)), 0, pic[80]);
338 sysbus_connect_irq(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 338, __func__)), 1, pic[81]);
339 sysbus_connect_irq(SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 339, __func__)), 2, pic[82]);
340 }
341
342 highbank_binfo.ram_size = ram_size;
343 highbank_binfo.kernel_filename = kernel_filename;
344 highbank_binfo.kernel_cmdline = kernel_cmdline;
345 highbank_binfo.initrd_filename = initrd_filename;
346 /* highbank requires a dtb in order to boot, and the dtb will override
347 * the board ID. The following value is ignored, so set it to -1 to be
348 * clear that the value is meaningless.
349 */
350 highbank_binfo.board_id = -1;
351 highbank_binfo.nb_cpus = smp_cpus;
352 highbank_binfo.loader_start = 0;
353 highbank_binfo.write_secondary_boot = hb_write_secondary;
354 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
355 arm_load_kernel(ARM_CPU(first_cpu)((ARMCPU *)object_dynamic_cast_assert(((Object *)((((&cpus
)->tqh_first)))), ("arm-cpu"), "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/highbank.c"
, 355, __func__)), &highbank_binfo);
356}
357
358static void highbank_init(QEMUMachineInitArgs *args)
359{
360 calxeda_init(args, CALXEDA_HIGHBANK);
361}
362
363static void midway_init(QEMUMachineInitArgs *args)
364{
365 calxeda_init(args, CALXEDA_MIDWAY);
1
Calling 'calxeda_init'
→
366}
367
368static QEMUMachine highbank_machine = {
369 .name = "highbank",
370 .desc = "Calxeda Highbank (ECX-1000)",
371 .init = highbank_init,
372 .block_default_type = IF_SCSI,
373 .max_cpus = 4,
374};
375
376static QEMUMachine midway_machine = {
377 .name = "midway",
378 .desc = "Calxeda Midway (ECX-2000)",
379 .init = midway_init,
380 .block_default_type = IF_SCSI,
381 .max_cpus = 4,
382};
383
384static void calxeda_machines_init(void)
385{
386 qemu_register_machine(&highbank_machine);
387 qemu_register_machine(&midway_machine);
388}
389
390machine_init(calxeda_machines_init)static void __attribute__((constructor)) do_qemu_init_calxeda_machines_init
(void) { register_module_init(calxeda_machines_init, MODULE_INIT_MACHINE
); };