Bug Summary

File:hw/usb/hcd-xhci.c
Location:line 1245, column 23
Description:Value stored to 'fg' during its initialization is never read

Annotated Source Code

1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21#include "hw/hw.h"
22#include "qemu-timer.h"
23#include "hw/usb.h"
24#include "hw/pci.h"
25#include "hw/msi.h"
26#include "trace.h"
27
28//#define DEBUG_XHCI
29//#define DEBUG_DATA
30
31#ifdef DEBUG_XHCI
32#define DPRINTF(...)do {} while (0) fprintf(stderrstderr, __VA_ARGS__)
33#else
34#define DPRINTF(...)do {} while (0) do {} while (0)
35#endif
36#define FIXME()do { fprintf(stderr, "FIXME %s:%d\n", __func__, 36); abort();
} while (0) do { fprintf(stderrstderr, "FIXME %s:%d\n", \
37 __func__, __LINE__37); abort(); } while (0)
38
39#define MAXSLOTS8 8
40#define MAXINTRS1 1
41
42#define USB2_PORTS4 4
43#define USB3_PORTS4 4
44
45#define MAXPORTS(4 +4) (USB2_PORTS4+USB3_PORTS4)
46
47#define TD_QUEUE24 24
48#define BG_XFERS8 8
49#define BG_PKTS8 8
50
51/* Very pessimistic, let's hope it's enough for all cases */
52#define EV_QUEUE(((3*24)+16)*8) (((3*TD_QUEUE24)+16)*MAXSLOTS8)
53/* Do not deliver ER Full events. NEC's driver does some things not bound
54 * to the specs when it gets them */
55#define ER_FULL_HACK
56
57#define LEN_CAP0x40 0x40
58#define OFF_OPER0x40 LEN_CAP0x40
59#define LEN_OPER(0x400 + 0x10 * (4 +4)) (0x400 + 0x10 * MAXPORTS(4 +4))
60#define OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) ((OFF_OPER0x40 + LEN_OPER(0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f)
61#define LEN_RUNTIME(0x20 + 1 * 0x20) (0x20 + MAXINTRS1 * 0x20)
62#define OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)) (OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + LEN_RUNTIME(0x20 + 1 * 0x20))
63#define LEN_DOORBELL((8 + 1) * 0x20) ((MAXSLOTS8 + 1) * 0x20)
64
65/* must be power of 2 */
66#define LEN_REGS0x2000 0x2000
67
68#if (OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)) + LEN_DOORBELL((8 + 1) * 0x20)) > LEN_REGS0x2000
69# error Increase LEN_REGS0x2000
70#endif
71
72#if MAXINTRS1 > 1
73# error TODO: only one interrupter supported
74#endif
75
76/* bit definitions */
77#define USBCMD_RS(1<<0) (1<<0)
78#define USBCMD_HCRST(1<<1) (1<<1)
79#define USBCMD_INTE(1<<2) (1<<2)
80#define USBCMD_HSEE(1<<3) (1<<3)
81#define USBCMD_LHCRST(1<<7) (1<<7)
82#define USBCMD_CSS(1<<8) (1<<8)
83#define USBCMD_CRS(1<<9) (1<<9)
84#define USBCMD_EWE(1<<10) (1<<10)
85#define USBCMD_EU3S(1<<11) (1<<11)
86
87#define USBSTS_HCH(1<<0) (1<<0)
88#define USBSTS_HSE(1<<2) (1<<2)
89#define USBSTS_EINT(1<<3) (1<<3)
90#define USBSTS_PCD(1<<4) (1<<4)
91#define USBSTS_SSS(1<<8) (1<<8)
92#define USBSTS_RSS(1<<9) (1<<9)
93#define USBSTS_SRE(1<<10) (1<<10)
94#define USBSTS_CNR(1<<11) (1<<11)
95#define USBSTS_HCE(1<<12) (1<<12)
96
97
98#define PORTSC_CCS(1<<0) (1<<0)
99#define PORTSC_PED(1<<1) (1<<1)
100#define PORTSC_OCA(1<<3) (1<<3)
101#define PORTSC_PR(1<<4) (1<<4)
102#define PORTSC_PLS_SHIFT5 5
103#define PORTSC_PLS_MASK0xf 0xf
104#define PORTSC_PP(1<<9) (1<<9)
105#define PORTSC_SPEED_SHIFT10 10
106#define PORTSC_SPEED_MASK0xf 0xf
107#define PORTSC_SPEED_FULL(1<<10) (1<<10)
108#define PORTSC_SPEED_LOW(2<<10) (2<<10)
109#define PORTSC_SPEED_HIGH(3<<10) (3<<10)
110#define PORTSC_SPEED_SUPER(4<<10) (4<<10)
111#define PORTSC_PIC_SHIFT14 14
112#define PORTSC_PIC_MASK0x3 0x3
113#define PORTSC_LWS(1<<16) (1<<16)
114#define PORTSC_CSC(1<<17) (1<<17)
115#define PORTSC_PEC(1<<18) (1<<18)
116#define PORTSC_WRC(1<<19) (1<<19)
117#define PORTSC_OCC(1<<20) (1<<20)
118#define PORTSC_PRC(1<<21) (1<<21)
119#define PORTSC_PLC(1<<22) (1<<22)
120#define PORTSC_CEC(1<<23) (1<<23)
121#define PORTSC_CAS(1<<24) (1<<24)
122#define PORTSC_WCE(1<<25) (1<<25)
123#define PORTSC_WDE(1<<26) (1<<26)
124#define PORTSC_WOE(1<<27) (1<<27)
125#define PORTSC_DR(1<<30) (1<<30)
126#define PORTSC_WPR(1<<31) (1<<31)
127
128#define CRCR_RCS(1<<0) (1<<0)
129#define CRCR_CS(1<<1) (1<<1)
130#define CRCR_CA(1<<2) (1<<2)
131#define CRCR_CRR(1<<3) (1<<3)
132
133#define IMAN_IP(1<<0) (1<<0)
134#define IMAN_IE(1<<1) (1<<1)
135
136#define ERDP_EHB(1<<3) (1<<3)
137
138#define TRB_SIZE16 16
139typedef struct XHCITRB {
140 uint64_t parameter;
141 uint32_t status;
142 uint32_t control;
143 dma_addr_t addr;
144 bool_Bool ccs;
145} XHCITRB;
146
147
148typedef enum TRBType {
149 TRB_RESERVED = 0,
150 TR_NORMAL,
151 TR_SETUP,
152 TR_DATA,
153 TR_STATUS,
154 TR_ISOCH,
155 TR_LINK,
156 TR_EVDATA,
157 TR_NOOP,
158 CR_ENABLE_SLOT,
159 CR_DISABLE_SLOT,
160 CR_ADDRESS_DEVICE,
161 CR_CONFIGURE_ENDPOINT,
162 CR_EVALUATE_CONTEXT,
163 CR_RESET_ENDPOINT,
164 CR_STOP_ENDPOINT,
165 CR_SET_TR_DEQUEUE,
166 CR_RESET_DEVICE,
167 CR_FORCE_EVENT,
168 CR_NEGOTIATE_BW,
169 CR_SET_LATENCY_TOLERANCE,
170 CR_GET_PORT_BANDWIDTH,
171 CR_FORCE_HEADER,
172 CR_NOOP,
173 ER_TRANSFER = 32,
174 ER_COMMAND_COMPLETE,
175 ER_PORT_STATUS_CHANGE,
176 ER_BANDWIDTH_REQUEST,
177 ER_DOORBELL,
178 ER_HOST_CONTROLLER,
179 ER_DEVICE_NOTIFICATION,
180 ER_MFINDEX_WRAP,
181 /* vendor specific bits */
182 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
183 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
184 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
185} TRBType;
186
187#define CR_LINKTR_LINK TR_LINK
188
189typedef enum TRBCCode {
190 CC_INVALID = 0,
191 CC_SUCCESS,
192 CC_DATA_BUFFER_ERROR,
193 CC_BABBLE_DETECTED,
194 CC_USB_TRANSACTION_ERROR,
195 CC_TRB_ERROR,
196 CC_STALL_ERROR,
197 CC_RESOURCE_ERROR,
198 CC_BANDWIDTH_ERROR,
199 CC_NO_SLOTS_ERROR,
200 CC_INVALID_STREAM_TYPE_ERROR,
201 CC_SLOT_NOT_ENABLED_ERROR,
202 CC_EP_NOT_ENABLED_ERROR,
203 CC_SHORT_PACKET,
204 CC_RING_UNDERRUN,
205 CC_RING_OVERRUN,
206 CC_VF_ER_FULL,
207 CC_PARAMETER_ERROR,
208 CC_BANDWIDTH_OVERRUN,
209 CC_CONTEXT_STATE_ERROR,
210 CC_NO_PING_RESPONSE_ERROR,
211 CC_EVENT_RING_FULL_ERROR,
212 CC_INCOMPATIBLE_DEVICE_ERROR,
213 CC_MISSED_SERVICE_ERROR,
214 CC_COMMAND_RING_STOPPED,
215 CC_COMMAND_ABORTED,
216 CC_STOPPED,
217 CC_STOPPED_LENGTH_INVALID,
218 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
219 CC_ISOCH_BUFFER_OVERRUN = 31,
220 CC_EVENT_LOST_ERROR,
221 CC_UNDEFINED_ERROR,
222 CC_INVALID_STREAM_ID_ERROR,
223 CC_SECONDARY_BANDWIDTH_ERROR,
224 CC_SPLIT_TRANSACTION_ERROR
225} TRBCCode;
226
227#define TRB_C(1<<0) (1<<0)
228#define TRB_TYPE_SHIFT10 10
229#define TRB_TYPE_MASK0x3f 0x3f
230#define TRB_TYPE(t)(((t).control >> 10) & 0x3f) (((t).control >> TRB_TYPE_SHIFT10) & TRB_TYPE_MASK0x3f)
231
232#define TRB_EV_ED(1<<2) (1<<2)
233
234#define TRB_TR_ENT(1<<1) (1<<1)
235#define TRB_TR_ISP(1<<2) (1<<2)
236#define TRB_TR_NS(1<<3) (1<<3)
237#define TRB_TR_CH(1<<4) (1<<4)
238#define TRB_TR_IOC(1<<5) (1<<5)
239#define TRB_TR_IDT(1<<6) (1<<6)
240#define TRB_TR_TBC_SHIFT7 7
241#define TRB_TR_TBC_MASK0x3 0x3
242#define TRB_TR_BEI(1<<9) (1<<9)
243#define TRB_TR_TLBPC_SHIFT16 16
244#define TRB_TR_TLBPC_MASK0xf 0xf
245#define TRB_TR_FRAMEID_SHIFT20 20
246#define TRB_TR_FRAMEID_MASK0x7ff 0x7ff
247#define TRB_TR_SIA(1<<31) (1<<31)
248
249#define TRB_TR_DIR(1<<16) (1<<16)
250
251#define TRB_CR_SLOTID_SHIFT24 24
252#define TRB_CR_SLOTID_MASK0xff 0xff
253#define TRB_CR_EPID_SHIFT16 16
254#define TRB_CR_EPID_MASK0x1f 0x1f
255
256#define TRB_CR_BSR(1<<9) (1<<9)
257#define TRB_CR_DC(1<<9) (1<<9)
258
259#define TRB_LK_TC(1<<1) (1<<1)
260
261#define EP_TYPE_MASK0x7 0x7
262#define EP_TYPE_SHIFT3 3
263
264#define EP_STATE_MASK0x7 0x7
265#define EP_DISABLED(0<<0) (0<<0)
266#define EP_RUNNING(1<<0) (1<<0)
267#define EP_HALTED(2<<0) (2<<0)
268#define EP_STOPPED(3<<0) (3<<0)
269#define EP_ERROR(4<<0) (4<<0)
270
271#define SLOT_STATE_MASK0x1f 0x1f
272#define SLOT_STATE_SHIFT27 27
273#define SLOT_STATE(s)(((s)>>27)&0x1f) (((s)>>SLOT_STATE_SHIFT27)&SLOT_STATE_MASK0x1f)
274#define SLOT_ENABLED0 0
275#define SLOT_DEFAULT1 1
276#define SLOT_ADDRESSED2 2
277#define SLOT_CONFIGURED3 3
278
279#define SLOT_CONTEXT_ENTRIES_MASK0x1f 0x1f
280#define SLOT_CONTEXT_ENTRIES_SHIFT27 27
281
282typedef enum EPType {
283 ET_INVALID = 0,
284 ET_ISO_OUT,
285 ET_BULK_OUT,
286 ET_INTR_OUT,
287 ET_CONTROL,
288 ET_ISO_IN,
289 ET_BULK_IN,
290 ET_INTR_IN,
291} EPType;
292
293typedef struct XHCIRing {
294 dma_addr_t base;
295 dma_addr_t dequeue;
296 bool_Bool ccs;
297} XHCIRing;
298
299typedef struct XHCIPort {
300 USBPort port;
301 uint32_t portsc;
302} XHCIPort;
303
304struct XHCIState;
305typedef struct XHCIState XHCIState;
306
307typedef struct XHCITransfer {
308 XHCIState *xhci;
309 USBPacket packet;
310 bool_Bool running_async;
311 bool_Bool running_retry;
312 bool_Bool cancelled;
313 bool_Bool complete;
314 bool_Bool backgrounded;
315 unsigned int iso_pkts;
316 unsigned int slotid;
317 unsigned int epid;
318 bool_Bool in_xfer;
319 bool_Bool iso_xfer;
320 bool_Bool bg_xfer;
321
322 unsigned int trb_count;
323 unsigned int trb_alloced;
324 XHCITRB *trbs;
325
326 unsigned int data_length;
327 unsigned int data_alloced;
328 uint8_t *data;
329
330 TRBCCode status;
331
332 unsigned int pkts;
333 unsigned int pktsize;
334 unsigned int cur_pkt;
335} XHCITransfer;
336
337typedef struct XHCIEPContext {
338 XHCIRing ring;
339 unsigned int next_xfer;
340 unsigned int comp_xfer;
341 XHCITransfer transfers[TD_QUEUE24];
342 XHCITransfer *retry;
343 bool_Bool bg_running;
344 bool_Bool bg_updating;
345 unsigned int next_bg;
346 XHCITransfer bg_transfers[BG_XFERS8];
347 EPType type;
348 dma_addr_t pctx;
349 unsigned int max_psize;
350 bool_Bool has_bg;
351 uint32_t state;
352} XHCIEPContext;
353
354typedef struct XHCISlot {
355 bool_Bool enabled;
356 dma_addr_t ctx;
357 unsigned int port;
358 unsigned int devaddr;
359 XHCIEPContext * eps[31];
360} XHCISlot;
361
362typedef struct XHCIEvent {
363 TRBType type;
364 TRBCCode ccode;
365 uint64_t ptr;
366 uint32_t length;
367 uint32_t flags;
368 uint8_t slotid;
369 uint8_t epid;
370} XHCIEvent;
371
372struct XHCIState {
373 PCIDevice pci_dev;
374 USBBus bus;
375 qemu_irq irq;
376 MemoryRegion mem;
377 const char *name;
378 uint32_t msi;
379 unsigned int devaddr;
380
381 /* Operational Registers */
382 uint32_t usbcmd;
383 uint32_t usbsts;
384 uint32_t dnctrl;
385 uint32_t crcr_low;
386 uint32_t crcr_high;
387 uint32_t dcbaap_low;
388 uint32_t dcbaap_high;
389 uint32_t config;
390
391 XHCIPort ports[MAXPORTS(4 +4)];
392 XHCISlot slots[MAXSLOTS8];
393
394 /* Runtime Registers */
395 uint32_t mfindex;
396 /* note: we only support one interrupter */
397 uint32_t iman;
398 uint32_t imod;
399 uint32_t erstsz;
400 uint32_t erstba_low;
401 uint32_t erstba_high;
402 uint32_t erdp_low;
403 uint32_t erdp_high;
404
405 dma_addr_t er_start;
406 uint32_t er_size;
407 bool_Bool er_pcs;
408 unsigned int er_ep_idx;
409 bool_Bool er_full;
410
411 XHCIEvent ev_buffer[EV_QUEUE(((3*24)+16)*8)];
412 unsigned int ev_buffer_put;
413 unsigned int ev_buffer_get;
414
415 XHCIRing cmd_ring;
416};
417
418typedef struct XHCIEvRingSeg {
419 uint32_t addr_low;
420 uint32_t addr_high;
421 uint32_t size;
422 uint32_t rsvd;
423} XHCIEvRingSeg;
424
425static const char *TRBType_names[] = {
426 [TRB_RESERVED] = "TRB_RESERVED",
427 [TR_NORMAL] = "TR_NORMAL",
428 [TR_SETUP] = "TR_SETUP",
429 [TR_DATA] = "TR_DATA",
430 [TR_STATUS] = "TR_STATUS",
431 [TR_ISOCH] = "TR_ISOCH",
432 [TR_LINK] = "TR_LINK",
433 [TR_EVDATA] = "TR_EVDATA",
434 [TR_NOOP] = "TR_NOOP",
435 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
436 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
437 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
438 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
439 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
440 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
441 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
442 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
443 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
444 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
445 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
446 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
447 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
448 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
449 [CR_NOOP] = "CR_NOOP",
450 [ER_TRANSFER] = "ER_TRANSFER",
451 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
452 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
453 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
454 [ER_DOORBELL] = "ER_DOORBELL",
455 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
456 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
457 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
458 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
459 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
460 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
461};
462
463static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
464{
465 if (index >= llen || list[index] == NULL((void*)0)) {
466 return "???";
467 }
468 return list[index];
469}
470
471static const char *trb_name(XHCITRB *trb)
472{
473 return lookup_name(TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f), TRBType_names,
474 ARRAY_SIZE(TRBType_names)(sizeof(TRBType_names) / sizeof((TRBType_names)[0])));
475}
476
477static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
478 unsigned int epid);
479
480static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
481{
482 if (sizeof(dma_addr_t) == 4) {
483 return low;
484 } else {
485 return low | (((dma_addr_t)high << 16) << 16);
486 }
487}
488
489static inline dma_addr_t xhci_mask64(uint64_t addr)
490{
491 if (sizeof(dma_addr_t) == 4) {
492 return addr & 0xffffffff;
493 } else {
494 return addr;
495 }
496}
497
498static void xhci_irq_update(XHCIState *xhci)
499{
500 int level = 0;
501
502 if (xhci->iman & IMAN_IP(1<<0) && xhci->iman & IMAN_IE(1<<1) &&
503 xhci->usbcmd & USBCMD_INTE(1<<2)) {
504 level = 1;
505 }
506
507 if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
508 if (level) {
509 trace_usb_xhci_irq_msi(0);
510 msi_notify(&xhci->pci_dev, 0);
511 }
512 } else {
513 trace_usb_xhci_irq_intx(level);
514 qemu_set_irq(xhci->irq, level);
515 }
516}
517
518static inline int xhci_running(XHCIState *xhci)
519{
520 return !(xhci->usbsts & USBSTS_HCH(1<<0)) && !xhci->er_full;
521}
522
523static void xhci_die(XHCIState *xhci)
524{
525 xhci->usbsts |= USBSTS_HCE(1<<12);
526 fprintf(stderrstderr, "xhci: asserted controller error\n");
527}
528
529static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
530{
531 XHCITRB ev_trb;
532 dma_addr_t addr;
533
534 ev_trb.parameter = cpu_to_le64(event->ptr);
535 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
536 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
537 event->flags | (event->type << TRB_TYPE_SHIFT10);
538 if (xhci->er_pcs) {
539 ev_trb.control |= TRB_C(1<<0);
540 }
541 ev_trb.control = cpu_to_le32(ev_trb.control);
542
543 trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb),
544 ev_trb.parameter, ev_trb.status, ev_trb.control);
545
546 addr = xhci->er_start + TRB_SIZE16*xhci->er_ep_idx;
547 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE16);
548
549 xhci->er_ep_idx++;
550 if (xhci->er_ep_idx >= xhci->er_size) {
551 xhci->er_ep_idx = 0;
552 xhci->er_pcs = !xhci->er_pcs;
553 }
554}
555
556static void xhci_events_update(XHCIState *xhci)
557{
558 dma_addr_t erdp;
559 unsigned int dp_idx;
560 bool_Bool do_irq = 0;
561
562 if (xhci->usbsts & USBSTS_HCH(1<<0)) {
563 return;
564 }
565
566 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
567 if (erdp < xhci->er_start ||
568 erdp >= (xhci->er_start + TRB_SIZE16*xhci->er_size)) {
569 fprintf(stderrstderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"%" "l" "x""\n", erdp);
570 fprintf(stderrstderr, "xhci: ER at "DMA_ADDR_FMT"%" "l" "x"" len %d\n",
571 xhci->er_start, xhci->er_size);
572 xhci_die(xhci);
573 return;
574 }
575 dp_idx = (erdp - xhci->er_start) / TRB_SIZE16;
576 assert(dp_idx < xhci->er_size)((dp_idx < xhci->er_size) ? (void) (0) : __assert_fail (
"dp_idx < xhci->er_size", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 576, __PRETTY_FUNCTION__));
577
578 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
579 * deadlocks when the ER is full. Hack it by holding off events until
580 * the driver decides to free at least half of the ring */
581 if (xhci->er_full) {
582 int er_free = dp_idx - xhci->er_ep_idx;
583 if (er_free <= 0) {
584 er_free += xhci->er_size;
585 }
586 if (er_free < (xhci->er_size/2)) {
587 DPRINTF("xhci_events_update(): event ring still "do {} while (0)
588 "more than half full (hack)\n")do {} while (0);
589 return;
590 }
591 }
592
593 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
594 assert(xhci->er_full)((xhci->er_full) ? (void) (0) : __assert_fail ("xhci->er_full"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 594
, __PRETTY_FUNCTION__));
595 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
596 DPRINTF("xhci_events_update(): event ring full again\n")do {} while (0);
597#ifndef ER_FULL_HACK
598 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
599 xhci_write_event(xhci, &full);
600#endif
601 do_irq = 1;
602 break;
603 }
604 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
605 xhci_write_event(xhci, event);
606 xhci->ev_buffer_get++;
607 do_irq = 1;
608 if (xhci->ev_buffer_get == EV_QUEUE(((3*24)+16)*8)) {
609 xhci->ev_buffer_get = 0;
610 }
611 }
612
613 if (do_irq) {
614 xhci->erdp_low |= ERDP_EHB(1<<3);
615 xhci->iman |= IMAN_IP(1<<0);
616 xhci->usbsts |= USBSTS_EINT(1<<3);
617 xhci_irq_update(xhci);
618 }
619
620 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
621 DPRINTF("xhci_events_update(): event ring no longer full\n")do {} while (0);
622 xhci->er_full = 0;
623 }
624 return;
625}
626
627static void xhci_event(XHCIState *xhci, XHCIEvent *event)
628{
629 dma_addr_t erdp;
630 unsigned int dp_idx;
631
632 if (xhci->er_full) {
633 DPRINTF("xhci_event(): ER full, queueing\n")do {} while (0);
634 if (((xhci->ev_buffer_put+1) % EV_QUEUE(((3*24)+16)*8)) == xhci->ev_buffer_get) {
635 fprintf(stderrstderr, "xhci: event queue full, dropping event!\n");
636 return;
637 }
638 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
639 if (xhci->ev_buffer_put == EV_QUEUE(((3*24)+16)*8)) {
640 xhci->ev_buffer_put = 0;
641 }
642 return;
643 }
644
645 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
646 if (erdp < xhci->er_start ||
647 erdp >= (xhci->er_start + TRB_SIZE16*xhci->er_size)) {
648 fprintf(stderrstderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"%" "l" "x""\n", erdp);
649 fprintf(stderrstderr, "xhci: ER at "DMA_ADDR_FMT"%" "l" "x"" len %d\n",
650 xhci->er_start, xhci->er_size);
651 xhci_die(xhci);
652 return;
653 }
654
655 dp_idx = (erdp - xhci->er_start) / TRB_SIZE16;
656 assert(dp_idx < xhci->er_size)((dp_idx < xhci->er_size) ? (void) (0) : __assert_fail (
"dp_idx < xhci->er_size", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 656, __PRETTY_FUNCTION__));
657
658 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
659 DPRINTF("xhci_event(): ER full, queueing\n")do {} while (0);
660#ifndef ER_FULL_HACK
661 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
662 xhci_write_event(xhci, &full);
663#endif
664 xhci->er_full = 1;
665 if (((xhci->ev_buffer_put+1) % EV_QUEUE(((3*24)+16)*8)) == xhci->ev_buffer_get) {
666 fprintf(stderrstderr, "xhci: event queue full, dropping event!\n");
667 return;
668 }
669 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
670 if (xhci->ev_buffer_put == EV_QUEUE(((3*24)+16)*8)) {
671 xhci->ev_buffer_put = 0;
672 }
673 } else {
674 xhci_write_event(xhci, event);
675 }
676
677 xhci->erdp_low |= ERDP_EHB(1<<3);
678 xhci->iman |= IMAN_IP(1<<0);
679 xhci->usbsts |= USBSTS_EINT(1<<3);
680
681 xhci_irq_update(xhci);
682}
683
684static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
685 dma_addr_t base)
686{
687 ring->base = base;
688 ring->dequeue = base;
689 ring->ccs = 1;
690}
691
692static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
693 dma_addr_t *addr)
694{
695 while (1) {
696 TRBType type;
697 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE16);
698 trb->addr = ring->dequeue;
699 trb->ccs = ring->ccs;
700 le64_to_cpus(&trb->parameter);
701 le32_to_cpus(&trb->status);
702 le32_to_cpus(&trb->control);
703
704 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
705 trb->parameter, trb->status, trb->control);
706
707 if ((trb->control & TRB_C(1<<0)) != ring->ccs) {
708 return 0;
709 }
710
711 type = TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f);
712
713 if (type != TR_LINK) {
714 if (addr) {
715 *addr = ring->dequeue;
716 }
717 ring->dequeue += TRB_SIZE16;
718 return type;
719 } else {
720 ring->dequeue = xhci_mask64(trb->parameter);
721 if (trb->control & TRB_LK_TC(1<<1)) {
722 ring->ccs = !ring->ccs;
723 }
724 }
725 }
726}
727
728static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
729{
730 XHCITRB trb;
731 int length = 0;
732 dma_addr_t dequeue = ring->dequeue;
733 bool_Bool ccs = ring->ccs;
734 /* hack to bundle together the two/three TDs that make a setup transfer */
735 bool_Bool control_td_set = 0;
736
737 while (1) {
738 TRBType type;
739 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE16);
740 le64_to_cpus(&trb.parameter);
741 le32_to_cpus(&trb.status);
742 le32_to_cpus(&trb.control);
743
744 if ((trb.control & TRB_C(1<<0)) != ccs) {
745 return -length;
746 }
747
748 type = TRB_TYPE(trb)(((trb).control >> 10) & 0x3f);
749
750 if (type == TR_LINK) {
751 dequeue = xhci_mask64(trb.parameter);
752 if (trb.control & TRB_LK_TC(1<<1)) {
753 ccs = !ccs;
754 }
755 continue;
756 }
757
758 length += 1;
759 dequeue += TRB_SIZE16;
760
761 if (type == TR_SETUP) {
762 control_td_set = 1;
763 } else if (type == TR_STATUS) {
764 control_td_set = 0;
765 }
766
767 if (!control_td_set && !(trb.control & TRB_TR_CH(1<<4))) {
768 return length;
769 }
770 }
771}
772
773static void xhci_er_reset(XHCIState *xhci)
774{
775 XHCIEvRingSeg seg;
776
777 /* cache the (sole) event ring segment location */
778 if (xhci->erstsz != 1) {
779 fprintf(stderrstderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
780 xhci_die(xhci);
781 return;
782 }
783 dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
784 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
785 le32_to_cpus(&seg.addr_low);
786 le32_to_cpus(&seg.addr_high);
787 le32_to_cpus(&seg.size);
788 if (seg.size < 16 || seg.size > 4096) {
789 fprintf(stderrstderr, "xhci: invalid value for segment size: %d\n", seg.size);
790 xhci_die(xhci);
791 return;
792 }
793 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
794 xhci->er_size = seg.size;
795
796 xhci->er_ep_idx = 0;
797 xhci->er_pcs = 1;
798 xhci->er_full = 0;
799
800 DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n",do {} while (0)
801 xhci->er_start, xhci->er_size)do {} while (0);
802}
803
804static void xhci_run(XHCIState *xhci)
805{
806 trace_usb_xhci_run();
807 xhci->usbsts &= ~USBSTS_HCH(1<<0);
808}
809
810static void xhci_stop(XHCIState *xhci)
811{
812 trace_usb_xhci_stop();
813 xhci->usbsts |= USBSTS_HCH(1<<0);
814 xhci->crcr_low &= ~CRCR_CRR(1<<3);
815}
816
817static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
818 uint32_t state)
819{
820 uint32_t ctx[5];
821 if (epctx->state == state) {
822 return;
823 }
824
825 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
826 ctx[0] &= ~EP_STATE_MASK0x7;
827 ctx[0] |= state;
828 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
829 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
830 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",do {} while (0)
831 epctx->pctx, state, ctx[3], ctx[2])do {} while (0);
832 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
833 epctx->state = state;
834}
835
836static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
837 unsigned int epid, dma_addr_t pctx,
838 uint32_t *ctx)
839{
840 XHCISlot *slot;
841 XHCIEPContext *epctx;
842 dma_addr_t dequeue;
843 int i;
844
845 trace_usb_xhci_ep_enable(slotid, epid);
846 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 846, __PRETTY_FUNCTION__));
847 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 847, __PRETTY_FUNCTION__));
848
849 slot = &xhci->slots[slotid-1];
850 if (slot->eps[epid-1]) {
851 fprintf(stderrstderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
852 return CC_TRB_ERROR;
853 }
854
855 epctx = g_malloc(sizeof(XHCIEPContext));
856 memset(epctx, 0, sizeof(XHCIEPContext));
857
858 slot->eps[epid-1] = epctx;
859
860 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
861 xhci_ring_init(xhci, &epctx->ring, dequeue);
862 epctx->ring.ccs = ctx[2] & 1;
863
864 epctx->type = (ctx[1] >> EP_TYPE_SHIFT3) & EP_TYPE_MASK0x7;
865 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type)do {} while (0);
866 epctx->pctx = pctx;
867 epctx->max_psize = ctx[1]>>16;
868 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
869 epctx->has_bg = false0;
870 if (epctx->type == ET_ISO_IN) {
871 epctx->has_bg = true1;
872 }
873 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",do {} while (0)
874 epid/2, epid%2, epctx->max_psize)do {} while (0);
875 for (i = 0; i < ARRAY_SIZE(epctx->transfers)(sizeof(epctx->transfers) / sizeof((epctx->transfers)[0
])); i++) {
876 usb_packet_init(&epctx->transfers[i].packet);
877 }
878
879 epctx->state = EP_RUNNING(1<<0);
880 ctx[0] &= ~EP_STATE_MASK0x7;
881 ctx[0] |= EP_RUNNING(1<<0);
882
883 return CC_SUCCESS;
884}
885
886static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
887 unsigned int epid)
888{
889 XHCISlot *slot;
890 XHCIEPContext *epctx;
891 int i, xferi, killed = 0;
892 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 892, __PRETTY_FUNCTION__));
893 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 893, __PRETTY_FUNCTION__));
894
895 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid)do {} while (0);
896
897 slot = &xhci->slots[slotid-1];
898
899 if (!slot->eps[epid-1]) {
900 return 0;
901 }
902
903 epctx = slot->eps[epid-1];
904
905 xferi = epctx->next_xfer;
906 for (i = 0; i < TD_QUEUE24; i++) {
907 XHCITransfer *t = &epctx->transfers[xferi];
908 if (t->running_async) {
909 usb_cancel_packet(&t->packet);
910 t->running_async = 0;
911 t->cancelled = 1;
912 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i)do {} while (0);
913 killed++;
914 }
915 if (t->running_retry) {
916 t->running_retry = 0;
917 epctx->retry = NULL((void*)0);
918 }
919 if (t->backgrounded) {
920 t->backgrounded = 0;
921 }
922 if (t->trbs) {
923 g_free(t->trbs);
924 }
925 if (t->data) {
926 g_free(t->data);
927 }
928
929 t->trbs = NULL((void*)0);
930 t->data = NULL((void*)0);
931 t->trb_count = t->trb_alloced = 0;
932 t->data_length = t->data_alloced = 0;
933 xferi = (xferi + 1) % TD_QUEUE24;
934 }
935 if (epctx->has_bg) {
936 xferi = epctx->next_bg;
937 for (i = 0; i < BG_XFERS8; i++) {
938 XHCITransfer *t = &epctx->bg_transfers[xferi];
939 if (t->running_async) {
940 usb_cancel_packet(&t->packet);
941 t->running_async = 0;
942 t->cancelled = 1;
943 DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i)do {} while (0);
944 killed++;
945 }
946 if (t->data) {
947 g_free(t->data);
948 }
949
950 t->data = NULL((void*)0);
951 xferi = (xferi + 1) % BG_XFERS8;
952 }
953 }
954 return killed;
955}
956
957static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
958 unsigned int epid)
959{
960 XHCISlot *slot;
961 XHCIEPContext *epctx;
962
963 trace_usb_xhci_ep_disable(slotid, epid);
964 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 964, __PRETTY_FUNCTION__));
965 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 965, __PRETTY_FUNCTION__));
966
967 slot = &xhci->slots[slotid-1];
968
969 if (!slot->eps[epid-1]) {
970 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid)do {} while (0);
971 return CC_SUCCESS;
972 }
973
974 xhci_ep_nuke_xfers(xhci, slotid, epid);
975
976 epctx = slot->eps[epid-1];
977
978 xhci_set_ep_state(xhci, epctx, EP_DISABLED(0<<0));
979
980 g_free(epctx);
981 slot->eps[epid-1] = NULL((void*)0);
982
983 return CC_SUCCESS;
984}
985
986static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
987 unsigned int epid)
988{
989 XHCISlot *slot;
990 XHCIEPContext *epctx;
991
992 trace_usb_xhci_ep_stop(slotid, epid);
993 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 993, __PRETTY_FUNCTION__));
994
995 if (epid < 1 || epid > 31) {
996 fprintf(stderrstderr, "xhci: bad ep %d\n", epid);
997 return CC_TRB_ERROR;
998 }
999
1000 slot = &xhci->slots[slotid-1];
1001
1002 if (!slot->eps[epid-1]) {
1003 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid)do {} while (0);
1004 return CC_EP_NOT_ENABLED_ERROR;
1005 }
1006
1007 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1008 fprintf(stderrstderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1009 "data might be lost\n");
1010 }
1011
1012 epctx = slot->eps[epid-1];
1013
1014 xhci_set_ep_state(xhci, epctx, EP_STOPPED(3<<0));
1015
1016 return CC_SUCCESS;
1017}
1018
1019static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1020 unsigned int epid)
1021{
1022 XHCISlot *slot;
1023 XHCIEPContext *epctx;
1024 USBDevice *dev;
1025
1026 trace_usb_xhci_ep_reset(slotid, epid);
1027 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1027, __PRETTY_FUNCTION__));
1028
1029 if (epid < 1 || epid > 31) {
1030 fprintf(stderrstderr, "xhci: bad ep %d\n", epid);
1031 return CC_TRB_ERROR;
1032 }
1033
1034 slot = &xhci->slots[slotid-1];
1035
1036 if (!slot->eps[epid-1]) {
1037 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid)do {} while (0);
1038 return CC_EP_NOT_ENABLED_ERROR;
1039 }
1040
1041 epctx = slot->eps[epid-1];
1042
1043 if (epctx->state != EP_HALTED(2<<0)) {
1044 fprintf(stderrstderr, "xhci: reset EP while EP %d not halted (%d)\n",
1045 epid, epctx->state);
1046 return CC_CONTEXT_STATE_ERROR;
1047 }
1048
1049 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1050 fprintf(stderrstderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1051 "data might be lost\n");
1052 }
1053
1054 uint8_t ep = epid>>1;
1055
1056 if (epid & 1) {
1057 ep |= 0x80;
1058 }
1059
1060 dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
1061 if (!dev) {
1062 return CC_USB_TRANSACTION_ERROR;
1063 }
1064
1065 xhci_set_ep_state(xhci, epctx, EP_STOPPED(3<<0));
1066
1067 return CC_SUCCESS;
1068}
1069
1070static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1071 unsigned int epid, uint64_t pdequeue)
1072{
1073 XHCISlot *slot;
1074 XHCIEPContext *epctx;
1075 dma_addr_t dequeue;
1076
1077 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1077, __PRETTY_FUNCTION__));
1078
1079 if (epid < 1 || epid > 31) {
1080 fprintf(stderrstderr, "xhci: bad ep %d\n", epid);
1081 return CC_TRB_ERROR;
1082 }
1083
1084 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue)do {} while (0);
1085 dequeue = xhci_mask64(pdequeue);
1086
1087 slot = &xhci->slots[slotid-1];
1088
1089 if (!slot->eps[epid-1]) {
1090 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid)do {} while (0);
1091 return CC_EP_NOT_ENABLED_ERROR;
1092 }
1093
1094 epctx = slot->eps[epid-1];
1095
1096
1097 if (epctx->state != EP_STOPPED(3<<0)) {
1098 fprintf(stderrstderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1099 return CC_CONTEXT_STATE_ERROR;
1100 }
1101
1102 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1103 epctx->ring.ccs = dequeue & 1;
1104
1105 xhci_set_ep_state(xhci, epctx, EP_STOPPED(3<<0));
1106
1107 return CC_SUCCESS;
1108}
1109
1110static int xhci_xfer_data(XHCITransfer *xfer, uint8_t *data,
1111 unsigned int length, bool_Bool in_xfer, bool_Bool out_xfer,
1112 bool_Bool report)
1113{
1114 int i;
1115 uint32_t edtla = 0;
1116 unsigned int transferred = 0;
1117 unsigned int left = length;
1118 bool_Bool reported = 0;
1119 bool_Bool shortpkt = 0;
1120 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1121 XHCIState *xhci = xfer->xhci;
1122
1123 DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",do {} while (0)
1124 length, in_xfer, out_xfer, report)do {} while (0);
1125
1126 assert(!(in_xfer && out_xfer))((!(in_xfer && out_xfer)) ? (void) (0) : __assert_fail
("!(in_xfer && out_xfer)", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1126, __PRETTY_FUNCTION__));
1127
1128 for (i = 0; i < xfer->trb_count; i++) {
1129 XHCITRB *trb = &xfer->trbs[i];
1130 dma_addr_t addr;
1131 unsigned int chunk = 0;
1132
1133 switch (TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f)) {
1134 case TR_DATA:
1135 if ((!(trb->control & TRB_TR_DIR(1<<16))) != (!in_xfer)) {
1136 fprintf(stderrstderr, "xhci: data direction mismatch for TR_DATA\n");
1137 xhci_die(xhci);
1138 return transferred;
1139 }
1140 /* fallthrough */
1141 case TR_NORMAL:
1142 case TR_ISOCH:
1143 addr = xhci_mask64(trb->parameter);
1144 chunk = trb->status & 0x1ffff;
1145 if (chunk > left) {
1146 chunk = left;
1147 shortpkt = 1;
1148 }
1149 if (in_xfer || out_xfer) {
1150 if (trb->control & TRB_TR_IDT(1<<6)) {
1151 uint64_t idata;
1152 if (chunk > 8 || in_xfer) {
1153 fprintf(stderrstderr, "xhci: invalid immediate data TRB\n");
1154 xhci_die(xhci);
1155 return transferred;
1156 }
1157 idata = le64_to_cpu(trb->parameter);
1158 memcpy(data, &idata, chunk);
1159 } else {
1160 DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "do {} while (0)
1161 DMA_ADDR_FMT "\n", in_xfer, chunk, addr)do {} while (0);
1162 if (in_xfer) {
1163 pci_dma_write(&xhci->pci_dev, addr, data, chunk);
1164 } else {
1165 pci_dma_read(&xhci->pci_dev, addr, data, chunk);
1166 }
1167#ifdef DEBUG_DATA
1168 unsigned int count = chunk;
1169 int i;
1170 if (count > 16) {
1171 count = 16;
1172 }
1173 DPRINTF(" ::")do {} while (0);
1174 for (i = 0; i < count; i++) {
1175 DPRINTF(" %02x", data[i])do {} while (0);
1176 }
1177 DPRINTF("\n")do {} while (0);
1178#endif
1179 }
1180 }
1181 left -= chunk;
1182 data += chunk;
1183 edtla += chunk;
1184 transferred += chunk;
1185 break;
1186 case TR_STATUS:
1187 reported = 0;
1188 shortpkt = 0;
1189 break;
1190 }
1191
1192 if (report && !reported && (trb->control & TRB_TR_IOC(1<<5) ||
1193 (shortpkt && (trb->control & TRB_TR_ISP(1<<2))))) {
1194 event.slotid = xfer->slotid;
1195 event.epid = xfer->epid;
1196 event.length = (trb->status & 0x1ffff) - chunk;
1197 event.flags = 0;
1198 event.ptr = trb->addr;
1199 if (xfer->status == CC_SUCCESS) {
1200 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1201 } else {
1202 event.ccode = xfer->status;
1203 }
1204 if (TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f) == TR_EVDATA) {
1205 event.ptr = trb->parameter;
1206 event.flags |= TRB_EV_ED(1<<2);
1207 event.length = edtla & 0xffffff;
1208 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length)do {} while (0);
1209 edtla = 0;
1210 }
1211 xhci_event(xhci, &event);
1212 reported = 1;
1213 }
1214 }
1215 return transferred;
1216}
1217
1218static void xhci_stall_ep(XHCITransfer *xfer)
1219{
1220 XHCIState *xhci = xfer->xhci;
1221 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1222 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1223
1224 epctx->ring.dequeue = xfer->trbs[0].addr;
1225 epctx->ring.ccs = xfer->trbs[0].ccs;
1226 xhci_set_ep_state(xhci, epctx, EP_HALTED(2<<0));
1227 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid)do {} while (0);
1228 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue)do {} while (0);
1229}
1230
1231static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1232 XHCIEPContext *epctx);
1233
1234static void xhci_bg_update(XHCIState *xhci, XHCIEPContext *epctx)
1235{
1236 if (epctx->bg_updating) {
1237 return;
1238 }
1239 DPRINTF("xhci_bg_update(%p, %p)\n", xhci, epctx)do {} while (0);
1240 assert(epctx->has_bg)((epctx->has_bg) ? (void) (0) : __assert_fail ("epctx->has_bg"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1240
, __PRETTY_FUNCTION__));
1241 DPRINTF("xhci: fg=%d bg=%d\n", epctx->comp_xfer, epctx->next_bg)do {} while (0);
1242 epctx->bg_updating = 1;
1243 while (epctx->transfers[epctx->comp_xfer].backgrounded &&
1244 epctx->bg_transfers[epctx->next_bg].complete) {
1245 XHCITransfer *fg = &epctx->transfers[epctx->comp_xfer];
Value stored to 'fg' during its initialization is never read
1246 XHCITransfer *bg = &epctx->bg_transfers[epctx->next_bg];
1247#if 0
1248 DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",do {} while (0)
1249 epctx->comp_xfer, epctx->next_bg, bg->cur_pkt,do {} while (0)
1250 bg->usbxfer->iso_packet_desc[bg->cur_pkt].statusdo {} while (0)
1251 )do {} while (0);
1252#endif
1253 assert(epctx->type == ET_ISO_IN)((epctx->type == ET_ISO_IN) ? (void) (0) : __assert_fail (
"epctx->type == ET_ISO_IN", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1253, __PRETTY_FUNCTION__));
1254 assert(bg->iso_xfer)((bg->iso_xfer) ? (void) (0) : __assert_fail ("bg->iso_xfer"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1254
, __PRETTY_FUNCTION__));
1255 assert(bg->in_xfer)((bg->in_xfer) ? (void) (0) : __assert_fail ("bg->in_xfer"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1255
, __PRETTY_FUNCTION__));
1256 uint8_t *p = bg->data + bg->cur_pkt * bg->pktsize;
1257#if 0
1258 int len = bg->usbxfer->iso_packet_desc[bg->cur_pkt].actual_length;
1259 fg->status = libusb_to_ccode(bg->usbxfer->iso_packet_desc[bg->cur_pkt].status);
1260#else
1261 int len = 0;
1262 FIXME()do { fprintf(stderr, "FIXME %s:%d\n", __func__, 1262); abort(
); } while (0);
1263#endif
1264 fg->complete = 1;
1265 fg->backgrounded = 0;
1266
1267 if (fg->status == CC_STALL_ERROR) {
1268 xhci_stall_ep(fg);
1269 }
1270
1271 xhci_xfer_data(fg, p, len, 1, 0, 1);
1272
1273 epctx->comp_xfer++;
1274 if (epctx->comp_xfer == TD_QUEUE24) {
1275 epctx->comp_xfer = 0;
1276 }
1277 DPRINTF("next fg xfer: %d\n", epctx->comp_xfer)do {} while (0);
1278 bg->cur_pkt++;
1279 if (bg->cur_pkt == bg->pkts) {
1280 bg->complete = 0;
1281 if (xhci_submit(xhci, bg, epctx) < 0) {
1282 fprintf(stderrstderr, "xhci: bg resubmit failed\n");
1283 }
1284 epctx->next_bg++;
1285 if (epctx->next_bg == BG_XFERS8) {
1286 epctx->next_bg = 0;
1287 }
1288 DPRINTF("next bg xfer: %d\n", epctx->next_bg)do {} while (0);
1289
1290 xhci_kick_ep(xhci, fg->slotid, fg->epid);
1291 }
1292 }
1293 epctx->bg_updating = 0;
1294}
1295
1296#if 0
1297static void xhci_xfer_cb(struct libusb_transfer *transfer)
1298{
1299 XHCIState *xhci;
1300 XHCITransfer *xfer;
1301
1302 xfer = (XHCITransfer *)transfer->user_data;
1303 xhci = xfer->xhci;
1304
1305 DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer->slotid,do {} while (0)
1306 xfer->epid, transfer->status)do {} while (0);
1307
1308 assert(xfer->slotid >= 1 && xfer->slotid <= MAXSLOTS)((xfer->slotid >= 1 && xfer->slotid <= 8)
? (void) (0) : __assert_fail ("xfer->slotid >= 1 && xfer->slotid <= 8"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1308
, __PRETTY_FUNCTION__));
1309 assert(xfer->epid >= 1 && xfer->epid <= 31)((xfer->epid >= 1 && xfer->epid <= 31) ? (
void) (0) : __assert_fail ("xfer->epid >= 1 && xfer->epid <= 31"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1309
, __PRETTY_FUNCTION__));
1310
1311 if (xfer->cancelled) {
1312 DPRINTF("xhci: transfer cancelled, not reporting anything\n")do {} while (0);
1313 xfer->running = 0;
1314 return;
1315 }
1316
1317 XHCIEPContext *epctx;
1318 XHCISlot *slot;
1319 slot = &xhci->slots[xfer->slotid-1];
1320 assert(slot->eps[xfer->epid-1])((slot->eps[xfer->epid-1]) ? (void) (0) : __assert_fail
("slot->eps[xfer->epid-1]", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1320, __PRETTY_FUNCTION__));
1321 epctx = slot->eps[xfer->epid-1];
1322
1323 if (xfer->bg_xfer) {
1324 DPRINTF("xhci: background transfer, updating\n")do {} while (0);
1325 xfer->complete = 1;
1326 xfer->running = 0;
1327 xhci_bg_update(xhci, epctx);
1328 return;
1329 }
1330
1331 if (xfer->iso_xfer) {
1332 transfer->status = transfer->iso_packet_desc[0].status;
1333 transfer->actual_length = transfer->iso_packet_desc[0].actual_length;
1334 }
1335
1336 xfer->status = libusb_to_ccode(transfer->status);
1337
1338 xfer->complete = 1;
1339 xfer->running = 0;
1340
1341 if (transfer->status == LIBUSB_TRANSFER_STALL)
1342 xhci_stall_ep(xhci, epctx, xfer);
1343
1344 DPRINTF("xhci: transfer actual length = %d\n", transfer->actual_length)do {} while (0);
1345
1346 if (xfer->in_xfer) {
1347 if (xfer->epid == 1) {
1348 xhci_xfer_data(xhci, xfer, xfer->data + 8,
1349 transfer->actual_length, 1, 0, 1);
1350 } else {
1351 xhci_xfer_data(xhci, xfer, xfer->data,
1352 transfer->actual_length, 1, 0, 1);
1353 }
1354 } else {
1355 xhci_xfer_data(xhci, xfer, NULL((void*)0), transfer->actual_length, 0, 0, 1);
1356 }
1357
1358 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1359}
1360
1361static int xhci_hle_control(XHCIState *xhci, XHCITransfer *xfer,
1362 uint8_t bmRequestType, uint8_t bRequest,
1363 uint16_t wValue, uint16_t wIndex, uint16_t wLength)
1364{
1365 uint16_t type_req = (bmRequestType << 8) | bRequest;
1366
1367 switch (type_req) {
1368 case 0x0000 | USB_REQ_SET_CONFIGURATION0x09:
1369 DPRINTF("xhci: HLE switch configuration\n")do {} while (0);
1370 return xhci_switch_config(xhci, xfer->slotid, wValue) == 0;
1371 case 0x0100 | USB_REQ_SET_INTERFACE0x0B:
1372 DPRINTF("xhci: HLE set interface altsetting\n")do {} while (0);
1373 return xhci_set_iface_alt(xhci, xfer->slotid, wIndex, wValue) == 0;
1374 case 0x0200 | USB_REQ_CLEAR_FEATURE0x01:
1375 if (wValue == 0) { // endpoint halt
1376 DPRINTF("xhci: HLE clear halt\n")do {} while (0);
1377 return xhci_clear_halt(xhci, xfer->slotid, wIndex);
1378 }
1379 case 0x0000 | USB_REQ_SET_ADDRESS0x05:
1380 fprintf(stderrstderr, "xhci: warn: illegal SET_ADDRESS request\n");
1381 return 0;
1382 default:
1383 return 0;
1384 }
1385}
1386#endif
1387
1388static int xhci_setup_packet(XHCITransfer *xfer, USBDevice *dev)
1389{
1390 USBEndpoint *ep;
1391 int dir;
1392
1393 dir = xfer->in_xfer ? USB_TOKEN_IN0x69 : USB_TOKEN_OUT0xe1;
1394 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1395 usb_packet_setup(&xfer->packet, dir, ep);
1396 usb_packet_addbuf(&xfer->packet, xfer->data, xfer->data_length);
1397 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",do {} while (0)
1398 xfer->packet.pid, dev->addr, ep->nr)do {} while (0);
1399 return 0;
1400}
1401
1402static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1403{
1404 if (ret == USB_RET_ASYNC(-6)) {
1405 trace_usb_xhci_xfer_async(xfer);
1406 xfer->running_async = 1;
1407 xfer->running_retry = 0;
1408 xfer->complete = 0;
1409 xfer->cancelled = 0;
1410 return 0;
1411 } else if (ret == USB_RET_NAK(-2)) {
1412 trace_usb_xhci_xfer_nak(xfer);
1413 xfer->running_async = 0;
1414 xfer->running_retry = 1;
1415 xfer->complete = 0;
1416 xfer->cancelled = 0;
1417 return 0;
1418 } else {
1419 xfer->running_async = 0;
1420 xfer->running_retry = 0;
1421 xfer->complete = 1;
1422 }
1423
1424 if (ret >= 0) {
1425 xfer->status = CC_SUCCESS;
1426 xhci_xfer_data(xfer, xfer->data, ret, xfer->in_xfer, 0, 1);
1427 trace_usb_xhci_xfer_success(xfer, ret);
1428 return 0;
1429 }
1430
1431 /* error */
1432 trace_usb_xhci_xfer_error(xfer, ret);
1433 switch (ret) {
1434 case USB_RET_NODEV(-1):
1435 xfer->status = CC_USB_TRANSACTION_ERROR;
1436 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1437 xhci_stall_ep(xfer);
1438 break;
1439 case USB_RET_STALL(-3):
1440 xfer->status = CC_STALL_ERROR;
1441 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1442 xhci_stall_ep(xfer);
1443 break;
1444 default:
1445 fprintf(stderrstderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1446 FIXME()do { fprintf(stderr, "FIXME %s:%d\n", __func__, 1446); abort(
); } while (0);
1447 }
1448 return 0;
1449}
1450
1451static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
1452{
1453 if (!(port->portsc & PORTSC_PED(1<<1))) {
1454 return NULL((void*)0);
1455 }
1456 return usb_find_device(&port->port, addr);
1457}
1458
1459static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1460{
1461 XHCITRB *trb_setup, *trb_status;
1462 uint8_t bmRequestType;
1463 uint16_t wLength;
1464 XHCIPort *port;
1465 USBDevice *dev;
1466 int ret;
1467
1468 trb_setup = &xfer->trbs[0];
1469 trb_status = &xfer->trbs[xfer->trb_count-1];
1470
1471 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid,
1472 trb_setup->parameter >> 48);
1473
1474 /* at most one Event Data TRB allowed after STATUS */
1475 if (TRB_TYPE(*trb_status)(((*trb_status).control >> 10) & 0x3f) == TR_EVDATA && xfer->trb_count > 2) {
1476 trb_status--;
1477 }
1478
1479 /* do some sanity checks */
1480 if (TRB_TYPE(*trb_setup)(((*trb_setup).control >> 10) & 0x3f) != TR_SETUP) {
1481 fprintf(stderrstderr, "xhci: ep0 first TD not SETUP: %d\n",
1482 TRB_TYPE(*trb_setup)(((*trb_setup).control >> 10) & 0x3f));
1483 return -1;
1484 }
1485 if (TRB_TYPE(*trb_status)(((*trb_status).control >> 10) & 0x3f) != TR_STATUS) {
1486 fprintf(stderrstderr, "xhci: ep0 last TD not STATUS: %d\n",
1487 TRB_TYPE(*trb_status)(((*trb_status).control >> 10) & 0x3f));
1488 return -1;
1489 }
1490 if (!(trb_setup->control & TRB_TR_IDT(1<<6))) {
1491 fprintf(stderrstderr, "xhci: Setup TRB doesn't have IDT set\n");
1492 return -1;
1493 }
1494 if ((trb_setup->status & 0x1ffff) != 8) {
1495 fprintf(stderrstderr, "xhci: Setup TRB has bad length (%d)\n",
1496 (trb_setup->status & 0x1ffff));
1497 return -1;
1498 }
1499
1500 bmRequestType = trb_setup->parameter;
1501 wLength = trb_setup->parameter >> 48;
1502
1503 if (xfer->data && xfer->data_alloced < wLength) {
1504 xfer->data_alloced = 0;
1505 g_free(xfer->data);
1506 xfer->data = NULL((void*)0);
1507 }
1508 if (!xfer->data) {
1509 DPRINTF("xhci: alloc %d bytes data\n", wLength)do {} while (0);
1510 xfer->data = g_malloc(wLength+1);
1511 xfer->data_alloced = wLength;
1512 }
1513 xfer->data_length = wLength;
1514
1515 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1516 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1517 if (!dev) {
1518 fprintf(stderrstderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1519 xhci->slots[xfer->slotid-1].port);
1520 return -1;
1521 }
1522
1523 xfer->in_xfer = bmRequestType & USB_DIR_IN0x80;
1524 xfer->iso_xfer = false0;
1525
1526 xhci_setup_packet(xfer, dev);
1527 xfer->packet.parameter = trb_setup->parameter;
1528 if (!xfer->in_xfer) {
1529 xhci_xfer_data(xfer, xfer->data, wLength, 0, 1, 0);
1530 }
1531
1532 ret = usb_handle_packet(dev, &xfer->packet);
1533
1534 xhci_complete_packet(xfer, ret);
1535 if (!xfer->running_async && !xfer->running_retry) {
1536 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1537 }
1538 return 0;
1539}
1540
1541static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1542{
1543 XHCIPort *port;
1544 USBDevice *dev;
1545 int ret;
1546
1547 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid)do {} while (0);
1548
1549 xfer->in_xfer = epctx->type>>2;
1550
1551 if (xfer->data && xfer->data_alloced < xfer->data_length) {
1552 xfer->data_alloced = 0;
1553 g_free(xfer->data);
1554 xfer->data = NULL((void*)0);
1555 }
1556 if (!xfer->data && xfer->data_length) {
1557 DPRINTF("xhci: alloc %d bytes data\n", xfer->data_length)do {} while (0);
1558 xfer->data = g_malloc(xfer->data_length);
1559 xfer->data_alloced = xfer->data_length;
1560 }
1561 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1562 if (!xfer->bg_xfer) {
1563 xfer->pkts = 1;
1564 }
1565 } else {
1566 xfer->pkts = 0;
1567 }
1568
1569 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1570 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1571 if (!dev) {
1572 fprintf(stderrstderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1573 xhci->slots[xfer->slotid-1].port);
1574 return -1;
1575 }
1576
1577 xhci_setup_packet(xfer, dev);
1578
1579 switch(epctx->type) {
1580 case ET_INTR_OUT:
1581 case ET_INTR_IN:
1582 case ET_BULK_OUT:
1583 case ET_BULK_IN:
1584 break;
1585 case ET_ISO_OUT:
1586 case ET_ISO_IN:
1587 FIXME()do { fprintf(stderr, "FIXME %s:%d\n", __func__, 1587); abort(
); } while (0);
1588 break;
1589 default:
1590 fprintf(stderrstderr, "xhci: unknown or unhandled EP "
1591 "(type %d, in %d, ep %02x)\n",
1592 epctx->type, xfer->in_xfer, xfer->epid);
1593 return -1;
1594 }
1595
1596 if (!xfer->in_xfer) {
1597 xhci_xfer_data(xfer, xfer->data, xfer->data_length, 0, 1, 0);
1598 }
1599 ret = usb_handle_packet(dev, &xfer->packet);
1600
1601 xhci_complete_packet(xfer, ret);
1602 if (!xfer->running_async && !xfer->running_retry) {
1603 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1604 }
1605 return 0;
1606}
1607
1608static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1609{
1610 int i;
1611 unsigned int length = 0;
1612 XHCITRB *trb;
1613
1614 for (i = 0; i < xfer->trb_count; i++) {
1615 trb = &xfer->trbs[i];
1616 if (TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f) == TR_NORMAL || TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f) == TR_ISOCH) {
1617 length += trb->status & 0x1ffff;
1618 }
1619 }
1620
1621 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, length);
1622
1623 if (!epctx->has_bg) {
1624 xfer->data_length = length;
1625 xfer->backgrounded = 0;
1626 return xhci_submit(xhci, xfer, epctx);
1627 } else {
1628 if (!epctx->bg_running) {
1629 for (i = 0; i < BG_XFERS8; i++) {
1630 XHCITransfer *t = &epctx->bg_transfers[i];
1631 t->xhci = xhci;
1632 t->epid = xfer->epid;
1633 t->slotid = xfer->slotid;
1634 t->pkts = BG_PKTS8;
1635 t->pktsize = epctx->max_psize;
1636 t->data_length = t->pkts * t->pktsize;
1637 t->bg_xfer = 1;
1638 if (xhci_submit(xhci, t, epctx) < 0) {
1639 fprintf(stderrstderr, "xhci: bg submit failed\n");
1640 return -1;
1641 }
1642 }
1643 epctx->bg_running = 1;
1644 }
1645 xfer->backgrounded = 1;
1646 xhci_bg_update(xhci, epctx);
1647 return 0;
1648 }
1649}
1650
1651static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1652{
1653 XHCIEPContext *epctx;
1654 int length;
1655 int i;
1656
1657 trace_usb_xhci_ep_kick(slotid, epid);
1658 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1658, __PRETTY_FUNCTION__));
1659 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1659, __PRETTY_FUNCTION__));
1660
1661 if (!xhci->slots[slotid-1].enabled) {
1662 fprintf(stderrstderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1663 return;
1664 }
1665 epctx = xhci->slots[slotid-1].eps[epid-1];
1666 if (!epctx) {
1667 fprintf(stderrstderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1668 epid, slotid);
1669 return;
1670 }
1671
1672 if (epctx->retry) {
1673 /* retry nak'ed transfer */
1674 XHCITransfer *xfer = epctx->retry;
1675 int result;
1676
1677 trace_usb_xhci_xfer_retry(xfer);
1678 assert(xfer->running_retry)((xfer->running_retry) ? (void) (0) : __assert_fail ("xfer->running_retry"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1678
, __PRETTY_FUNCTION__));
1679 xhci_setup_packet(xfer, xfer->packet.ep->dev);
1680 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1681 if (result == USB_RET_NAK(-2)) {
1682 return;
1683 }
1684 xhci_complete_packet(xfer, result);
1685 assert(!xfer->running_retry)((!xfer->running_retry) ? (void) (0) : __assert_fail ("!xfer->running_retry"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1685
, __PRETTY_FUNCTION__));
1686 epctx->retry = NULL((void*)0);
1687 }
1688
1689 if (epctx->state == EP_HALTED(2<<0)) {
1690 DPRINTF("xhci: ep halted, not running schedule\n")do {} while (0);
1691 return;
1692 }
1693
1694 xhci_set_ep_state(xhci, epctx, EP_RUNNING(1<<0));
1695
1696 while (1) {
1697 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1698 if (xfer->running_async || xfer->running_retry || xfer->backgrounded) {
1699 break;
1700 }
1701 length = xhci_ring_chain_length(xhci, &epctx->ring);
1702 if (length < 0) {
1703 break;
1704 } else if (length == 0) {
1705 break;
1706 }
1707 if (xfer->trbs && xfer->trb_alloced < length) {
1708 xfer->trb_count = 0;
1709 xfer->trb_alloced = 0;
1710 g_free(xfer->trbs);
1711 xfer->trbs = NULL((void*)0);
1712 }
1713 if (!xfer->trbs) {
1714 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1715 xfer->trb_alloced = length;
1716 }
1717 xfer->trb_count = length;
1718
1719 for (i = 0; i < length; i++) {
1720 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL))((xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs
[i], ((void*)0))) ? (void) (0) : __assert_fail ("xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], ((void*)0))"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1720
, __PRETTY_FUNCTION__));
1721 }
1722 xfer->xhci = xhci;
1723 xfer->epid = epid;
1724 xfer->slotid = slotid;
1725
1726 if (epid == 1) {
1727 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1728 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE24;
1729 } else {
1730 fprintf(stderrstderr, "xhci: error firing CTL transfer\n");
1731 }
1732 } else {
1733 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1734 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE24;
1735 } else {
1736 fprintf(stderrstderr, "xhci: error firing data transfer\n");
1737 }
1738 }
1739
1740 if (epctx->state == EP_HALTED(2<<0)) {
1741 break;
1742 }
1743 if (xfer->running_retry) {
1744 DPRINTF("xhci: xfer nacked, stopping schedule\n")do {} while (0);
1745 epctx->retry = xfer;
1746 break;
1747 }
1748 }
1749}
1750
1751static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1752{
1753 trace_usb_xhci_slot_enable(slotid);
1754 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1754, __PRETTY_FUNCTION__));
1755 xhci->slots[slotid-1].enabled = 1;
1756 xhci->slots[slotid-1].port = 0;
1757 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1758
1759 return CC_SUCCESS;
1760}
1761
1762static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1763{
1764 int i;
1765
1766 trace_usb_xhci_slot_disable(slotid);
1767 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1767, __PRETTY_FUNCTION__));
1768
1769 for (i = 1; i <= 31; i++) {
1770 if (xhci->slots[slotid-1].eps[i-1]) {
1771 xhci_disable_ep(xhci, slotid, i);
1772 }
1773 }
1774
1775 xhci->slots[slotid-1].enabled = 0;
1776 return CC_SUCCESS;
1777}
1778
1779static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1780 uint64_t pictx, bool_Bool bsr)
1781{
1782 XHCISlot *slot;
1783 USBDevice *dev;
1784 dma_addr_t ictx, octx, dcbaap;
1785 uint64_t poctx;
1786 uint32_t ictl_ctx[2];
1787 uint32_t slot_ctx[4];
1788 uint32_t ep0_ctx[5];
1789 unsigned int port;
1790 int i;
1791 TRBCCode res;
1792
1793 trace_usb_xhci_slot_address(slotid);
1794 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1794, __PRETTY_FUNCTION__));
1795
1796 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
1797 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx));
1798 ictx = xhci_mask64(pictx);
1799 octx = xhci_mask64(le64_to_cpu(poctx));
1800
1801 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx)do {} while (0);
1802 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
1803
1804 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1805
1806 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1807 fprintf(stderrstderr, "xhci: invalid input context control %08x %08x\n",
1808 ictl_ctx[0], ictl_ctx[1]);
1809 return CC_TRB_ERROR;
1810 }
1811
1812 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx));
1813 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx));
1814
1815 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",do {} while (0)
1816 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
1817
1818 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
1819 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4])do {} while (0);
1820
1821 port = (slot_ctx[1]>>16) & 0xFF;
1822 dev = xhci->ports[port-1].port.dev;
1823
1824 if (port < 1 || port > MAXPORTS(4 +4)) {
1825 fprintf(stderrstderr, "xhci: bad port %d\n", port);
1826 return CC_TRB_ERROR;
1827 } else if (!dev) {
1828 fprintf(stderrstderr, "xhci: port %d not connected\n", port);
1829 return CC_USB_TRANSACTION_ERROR;
1830 }
1831
1832 for (i = 0; i < MAXSLOTS8; i++) {
1833 if (xhci->slots[i].port == port) {
1834 fprintf(stderrstderr, "xhci: port %d already assigned to slot %d\n",
1835 port, i+1);
1836 return CC_TRB_ERROR;
1837 }
1838 }
1839
1840 slot = &xhci->slots[slotid-1];
1841 slot->port = port;
1842 slot->ctx = octx;
1843
1844 if (bsr) {
1845 slot_ctx[3] = SLOT_DEFAULT1 << SLOT_STATE_SHIFT27;
1846 } else {
1847 slot->devaddr = xhci->devaddr++;
1848 slot_ctx[3] = (SLOT_ADDRESSED2 << SLOT_STATE_SHIFT27) | slot->devaddr;
1849 DPRINTF("xhci: device address is %d\n", slot->devaddr)do {} while (0);
1850 usb_device_handle_control(dev, NULL((void*)0),
1851 DeviceOutRequest((0|(0x00 << 5)|0x00)<<8) | USB_REQ_SET_ADDRESS0x05,
1852 slot->devaddr, 0, 0, NULL((void*)0));
1853 }
1854
1855 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1856
1857 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
1858 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
1859 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
1860 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4])do {} while (0);
1861
1862 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1863 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1864
1865 return res;
1866}
1867
1868
1869static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1870 uint64_t pictx, bool_Bool dc)
1871{
1872 dma_addr_t ictx, octx;
1873 uint32_t ictl_ctx[2];
1874 uint32_t slot_ctx[4];
1875 uint32_t islot_ctx[4];
1876 uint32_t ep_ctx[5];
1877 int i;
1878 TRBCCode res;
1879
1880 trace_usb_xhci_slot_configure(slotid);
1881 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1881, __PRETTY_FUNCTION__));
1882
1883 ictx = xhci_mask64(pictx);
1884 octx = xhci->slots[slotid-1].ctx;
1885
1886 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx)do {} while (0);
1887 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
1888
1889 if (dc) {
1890 for (i = 2; i <= 31; i++) {
1891 if (xhci->slots[slotid-1].eps[i-1]) {
1892 xhci_disable_ep(xhci, slotid, i);
1893 }
1894 }
1895
1896 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1897 slot_ctx[3] &= ~(SLOT_STATE_MASK0x1f << SLOT_STATE_SHIFT27);
1898 slot_ctx[3] |= SLOT_ADDRESSED2 << SLOT_STATE_SHIFT27;
1899 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
1900 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
1901 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1902
1903 return CC_SUCCESS;
1904 }
1905
1906 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1907
1908 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1909 fprintf(stderrstderr, "xhci: invalid input context control %08x %08x\n",
1910 ictl_ctx[0], ictl_ctx[1]);
1911 return CC_TRB_ERROR;
1912 }
1913
1914 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1915 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1916
1917 if (SLOT_STATE(slot_ctx[3])(((slot_ctx[3])>>27)&0x1f) < SLOT_ADDRESSED2) {
1918 fprintf(stderrstderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1919 return CC_CONTEXT_STATE_ERROR;
1920 }
1921
1922 for (i = 2; i <= 31; i++) {
1923 if (ictl_ctx[0] & (1<<i)) {
1924 xhci_disable_ep(xhci, slotid, i);
1925 }
1926 if (ictl_ctx[1] & (1<<i)) {
1927 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx,
1928 sizeof(ep_ctx));
1929 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",do {} while (0)
1930 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],do {} while (0)
1931 ep_ctx[3], ep_ctx[4])do {} while (0);
1932 xhci_disable_ep(xhci, slotid, i);
1933 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1934 if (res != CC_SUCCESS) {
1935 return res;
1936 }
1937 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",do {} while (0)
1938 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],do {} while (0)
1939 ep_ctx[3], ep_ctx[4])do {} while (0);
1940 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx));
1941 }
1942 }
1943
1944 slot_ctx[3] &= ~(SLOT_STATE_MASK0x1f << SLOT_STATE_SHIFT27);
1945 slot_ctx[3] |= SLOT_CONFIGURED3 << SLOT_STATE_SHIFT27;
1946 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK0x1f << SLOT_CONTEXT_ENTRIES_SHIFT27);
1947 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK0x1f <<
1948 SLOT_CONTEXT_ENTRIES_SHIFT27);
1949 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
1950 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
1951
1952 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1953
1954 return CC_SUCCESS;
1955}
1956
1957
1958static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1959 uint64_t pictx)
1960{
1961 dma_addr_t ictx, octx;
1962 uint32_t ictl_ctx[2];
1963 uint32_t iep0_ctx[5];
1964 uint32_t ep0_ctx[5];
1965 uint32_t islot_ctx[4];
1966 uint32_t slot_ctx[4];
1967
1968 trace_usb_xhci_slot_evaluate(slotid);
1969 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1969, __PRETTY_FUNCTION__));
1970
1971 ictx = xhci_mask64(pictx);
1972 octx = xhci->slots[slotid-1].ctx;
1973
1974 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx)do {} while (0);
1975 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
1976
1977 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1978
1979 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1980 fprintf(stderrstderr, "xhci: invalid input context control %08x %08x\n",
1981 ictl_ctx[0], ictl_ctx[1]);
1982 return CC_TRB_ERROR;
1983 }
1984
1985 if (ictl_ctx[1] & 0x1) {
1986 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1987
1988 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",do {} while (0)
1989 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3])do {} while (0);
1990
1991 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1992
1993 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1994 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1995 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1996 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1997
1998 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
1999 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2000
2001 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
2002 }
2003
2004 if (ictl_ctx[1] & 0x2) {
2005 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2006
2007 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
2008 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],do {} while (0)
2009 iep0_ctx[3], iep0_ctx[4])do {} while (0);
2010
2011 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
2012
2013 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2014 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2015
2016 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
2017 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4])do {} while (0);
2018
2019 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
2020 }
2021
2022 return CC_SUCCESS;
2023}
2024
2025static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2026{
2027 uint32_t slot_ctx[4];
2028 dma_addr_t octx;
2029 int i;
2030
2031 trace_usb_xhci_slot_reset(slotid);
2032 assert(slotid >= 1 && slotid <= MAXSLOTS)((slotid >= 1 && slotid <= 8) ? (void) (0) : __assert_fail
("slotid >= 1 && slotid <= 8", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2032, __PRETTY_FUNCTION__));
2033
2034 octx = xhci->slots[slotid-1].ctx;
2035
2036 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
2037
2038 for (i = 2; i <= 31; i++) {
2039 if (xhci->slots[slotid-1].eps[i-1]) {
2040 xhci_disable_ep(xhci, slotid, i);
2041 }
2042 }
2043
2044 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
2045 slot_ctx[3] &= ~(SLOT_STATE_MASK0x1f << SLOT_STATE_SHIFT27);
2046 slot_ctx[3] |= SLOT_DEFAULT1 << SLOT_STATE_SHIFT27;
2047 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
2048 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2049 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
2050
2051 return CC_SUCCESS;
2052}
2053
2054static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2055{
2056 unsigned int slotid;
2057 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT24) & TRB_CR_SLOTID_MASK0xff;
2058 if (slotid < 1 || slotid > MAXSLOTS8) {
2059 fprintf(stderrstderr, "xhci: bad slot id %d\n", slotid);
2060 event->ccode = CC_TRB_ERROR;
2061 return 0;
2062 } else if (!xhci->slots[slotid-1].enabled) {
2063 fprintf(stderrstderr, "xhci: slot id %d not enabled\n", slotid);
2064 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2065 return 0;
2066 }
2067 return slotid;
2068}
2069
2070static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2071{
2072 dma_addr_t ctx;
2073 uint8_t bw_ctx[MAXPORTS(4 +4)+1];
2074
2075 DPRINTF("xhci_get_port_bandwidth()\n")do {} while (0);
2076
2077 ctx = xhci_mask64(pctx);
2078
2079 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx)do {} while (0);
2080
2081 /* TODO: actually implement real values here */
2082 bw_ctx[0] = 0;
2083 memset(&bw_ctx[1], 80, MAXPORTS(4 +4)); /* 80% */
2084 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
2085
2086 return CC_SUCCESS;
2087}
2088
2089static uint32_t rotl(uint32_t v, unsigned count)
2090{
2091 count &= 31;
2092 return (v << count) | (v >> (32 - count));
2093}
2094
2095
2096static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2097{
2098 uint32_t val;
2099 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2100 val += rotl(lo + 0x49434878, hi & 0x1F);
2101 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2102 return ~val;
2103}
2104
2105static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2106{
2107 uint32_t buf[8];
2108 uint32_t obuf[8];
2109 dma_addr_t paddr = xhci_mask64(addr);
2110
2111 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
2112
2113 memcpy(obuf, buf, sizeof(obuf));
2114
2115 if ((buf[0] & 0xff) == 2) {
2116 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2117 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2118 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2119 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2120 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2121 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2122 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2123 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2124 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2125 }
2126
2127 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
2128}
2129
2130static void xhci_process_commands(XHCIState *xhci)
2131{
2132 XHCITRB trb;
2133 TRBType type;
2134 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2135 dma_addr_t addr;
2136 unsigned int i, slotid = 0;
2137
2138 DPRINTF("xhci_process_commands()\n")do {} while (0);
2139 if (!xhci_running(xhci)) {
2140 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n")do {} while (0);
2141 return;
2142 }
2143
2144 xhci->crcr_low |= CRCR_CRR(1<<3);
2145
2146 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2147 event.ptr = addr;
2148 switch (type) {
2149 case CR_ENABLE_SLOT:
2150 for (i = 0; i < MAXSLOTS8; i++) {
2151 if (!xhci->slots[i].enabled) {
2152 break;
2153 }
2154 }
2155 if (i >= MAXSLOTS8) {
2156 fprintf(stderrstderr, "xhci: no device slots available\n");
2157 event.ccode = CC_NO_SLOTS_ERROR;
2158 } else {
2159 slotid = i+1;
2160 event.ccode = xhci_enable_slot(xhci, slotid);
2161 }
2162 break;
2163 case CR_DISABLE_SLOT:
2164 slotid = xhci_get_slot(xhci, &event, &trb);
2165 if (slotid) {
2166 event.ccode = xhci_disable_slot(xhci, slotid);
2167 }
2168 break;
2169 case CR_ADDRESS_DEVICE:
2170 slotid = xhci_get_slot(xhci, &event, &trb);
2171 if (slotid) {
2172 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2173 trb.control & TRB_CR_BSR(1<<9));
2174 }
2175 break;
2176 case CR_CONFIGURE_ENDPOINT:
2177 slotid = xhci_get_slot(xhci, &event, &trb);
2178 if (slotid) {
2179 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2180 trb.control & TRB_CR_DC(1<<9));
2181 }
2182 break;
2183 case CR_EVALUATE_CONTEXT:
2184 slotid = xhci_get_slot(xhci, &event, &trb);
2185 if (slotid) {
2186 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2187 }
2188 break;
2189 case CR_STOP_ENDPOINT:
2190 slotid = xhci_get_slot(xhci, &event, &trb);
2191 if (slotid) {
2192 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT16)
2193 & TRB_CR_EPID_MASK0x1f;
2194 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2195 }
2196 break;
2197 case CR_RESET_ENDPOINT:
2198 slotid = xhci_get_slot(xhci, &event, &trb);
2199 if (slotid) {
2200 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT16)
2201 & TRB_CR_EPID_MASK0x1f;
2202 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2203 }
2204 break;
2205 case CR_SET_TR_DEQUEUE:
2206 slotid = xhci_get_slot(xhci, &event, &trb);
2207 if (slotid) {
2208 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT16)
2209 & TRB_CR_EPID_MASK0x1f;
2210 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2211 trb.parameter);
2212 }
2213 break;
2214 case CR_RESET_DEVICE:
2215 slotid = xhci_get_slot(xhci, &event, &trb);
2216 if (slotid) {
2217 event.ccode = xhci_reset_slot(xhci, slotid);
2218 }
2219 break;
2220 case CR_GET_PORT_BANDWIDTH:
2221 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2222 break;
2223 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2224 xhci_via_challenge(xhci, trb.parameter);
2225 break;
2226 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2227 event.type = 48; /* NEC reply */
2228 event.length = 0x3025;
2229 break;
2230 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2231 {
2232 uint32_t chi = trb.parameter >> 32;
2233 uint32_t clo = trb.parameter;
2234 uint32_t val = xhci_nec_challenge(chi, clo);
2235 event.length = val & 0xFFFF;
2236 event.epid = val >> 16;
2237 slotid = val >> 24;
2238 event.type = 48; /* NEC reply */
2239 }
2240 break;
2241 default:
2242 fprintf(stderrstderr, "xhci: unimplemented command %d\n", type);
2243 event.ccode = CC_TRB_ERROR;
2244 break;
2245 }
2246 event.slotid = slotid;
2247 xhci_event(xhci, &event);
2248 }
2249}
2250
2251static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2252{
2253 int nr = port->port.index + 1;
2254
2255 port->portsc = PORTSC_PP(1<<9);
2256 if (port->port.dev && port->port.dev->attached && !is_detach) {
2257 port->portsc |= PORTSC_CCS(1<<0);
2258 switch (port->port.dev->speed) {
2259 case USB_SPEED_LOW0:
2260 port->portsc |= PORTSC_SPEED_LOW(2<<10);
2261 break;
2262 case USB_SPEED_FULL1:
2263 port->portsc |= PORTSC_SPEED_FULL(1<<10);
2264 break;
2265 case USB_SPEED_HIGH2:
2266 port->portsc |= PORTSC_SPEED_HIGH(3<<10);
2267 break;
2268 }
2269 }
2270
2271 if (xhci_running(xhci)) {
2272 port->portsc |= PORTSC_CSC(1<<17);
2273 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2274 xhci_event(xhci, &ev);
2275 DPRINTF("xhci: port change event for port %d\n", nr)do {} while (0);
2276 }
2277}
2278
2279static void xhci_reset(DeviceState *dev)
2280{
2281 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(XHCIState, pci_dev.qdev)]; ({ const typeof
(((XHCIState *) 0)->pci_dev.qdev) *__mptr = (dev); (XHCIState
*) ((char *) __mptr - __builtin_offsetof(XHCIState, pci_dev.
qdev));});}));
2282 int i;
2283
2284 trace_usb_xhci_reset();
2285 if (!(xhci->usbsts & USBSTS_HCH(1<<0))) {
2286 fprintf(stderrstderr, "xhci: reset while running!\n");
2287 }
2288
2289 xhci->usbcmd = 0;
2290 xhci->usbsts = USBSTS_HCH(1<<0);
2291 xhci->dnctrl = 0;
2292 xhci->crcr_low = 0;
2293 xhci->crcr_high = 0;
2294 xhci->dcbaap_low = 0;
2295 xhci->dcbaap_high = 0;
2296 xhci->config = 0;
2297 xhci->devaddr = 2;
2298
2299 for (i = 0; i < MAXSLOTS8; i++) {
2300 xhci_disable_slot(xhci, i+1);
2301 }
2302
2303 for (i = 0; i < MAXPORTS(4 +4); i++) {
2304 xhci_update_port(xhci, xhci->ports + i, 0);
2305 }
2306
2307 xhci->mfindex = 0;
2308 xhci->iman = 0;
2309 xhci->imod = 0;
2310 xhci->erstsz = 0;
2311 xhci->erstba_low = 0;
2312 xhci->erstba_high = 0;
2313 xhci->erdp_low = 0;
2314 xhci->erdp_high = 0;
2315
2316 xhci->er_ep_idx = 0;
2317 xhci->er_pcs = 1;
2318 xhci->er_full = 0;
2319 xhci->ev_buffer_put = 0;
2320 xhci->ev_buffer_get = 0;
2321}
2322
2323static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2324{
2325 uint32_t ret;
2326
2327 switch (reg) {
2328 case 0x00: /* HCIVERSION, CAPLENGTH */
2329 ret = 0x01000000 | LEN_CAP0x40;
2330 break;
2331 case 0x04: /* HCSPARAMS 1 */
2332 ret = (MAXPORTS(4 +4)<<24) | (MAXINTRS1<<8) | MAXSLOTS8;
2333 break;
2334 case 0x08: /* HCSPARAMS 2 */
2335 ret = 0x0000000f;
2336 break;
2337 case 0x0c: /* HCSPARAMS 3 */
2338 ret = 0x00000000;
2339 break;
2340 case 0x10: /* HCCPARAMS */
2341 if (sizeof(dma_addr_t) == 4) {
2342 ret = 0x00081000;
2343 } else {
2344 ret = 0x00081001;
2345 }
2346 break;
2347 case 0x14: /* DBOFF */
2348 ret = OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20));
2349 break;
2350 case 0x18: /* RTSOFF */
2351 ret = OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f);
2352 break;
2353
2354 /* extended capabilities */
2355 case 0x20: /* Supported Protocol:00 */
2356 ret = 0x02000402; /* USB 2.0 */
2357 break;
2358 case 0x24: /* Supported Protocol:04 */
2359 ret = 0x20425455; /* "USB " */
2360 break;
2361 case 0x28: /* Supported Protocol:08 */
2362 ret = 0x00000001 | (USB2_PORTS4<<8);
2363 break;
2364 case 0x2c: /* Supported Protocol:0c */
2365 ret = 0x00000000; /* reserved */
2366 break;
2367 case 0x30: /* Supported Protocol:00 */
2368 ret = 0x03000002; /* USB 3.0 */
2369 break;
2370 case 0x34: /* Supported Protocol:04 */
2371 ret = 0x20425455; /* "USB " */
2372 break;
2373 case 0x38: /* Supported Protocol:08 */
2374 ret = 0x00000000 | (USB2_PORTS4+1) | (USB3_PORTS4<<8);
2375 break;
2376 case 0x3c: /* Supported Protocol:0c */
2377 ret = 0x00000000; /* reserved */
2378 break;
2379 default:
2380 fprintf(stderrstderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2381 ret = 0;
2382 }
2383
2384 trace_usb_xhci_cap_read(reg, ret);
2385 return ret;
2386}
2387
2388static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2389{
2390 uint32_t port = reg >> 4;
2391 uint32_t ret;
2392
2393 if (port >= MAXPORTS(4 +4)) {
2394 fprintf(stderrstderr, "xhci_port_read: port %d out of bounds\n", port);
2395 ret = 0;
2396 goto out;
2397 }
2398
2399 switch (reg & 0xf) {
2400 case 0x00: /* PORTSC */
2401 ret = xhci->ports[port].portsc;
2402 break;
2403 case 0x04: /* PORTPMSC */
2404 case 0x08: /* PORTLI */
2405 ret = 0;
2406 break;
2407 case 0x0c: /* reserved */
2408 default:
2409 fprintf(stderrstderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2410 port, reg);
2411 ret = 0;
2412 }
2413
2414out:
2415 trace_usb_xhci_port_read(port, reg & 0x0f, ret);
2416 return ret;
2417}
2418
2419static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2420{
2421 uint32_t port = reg >> 4;
2422 uint32_t portsc;
2423
2424 trace_usb_xhci_port_write(port, reg & 0x0f, val);
2425
2426 if (port >= MAXPORTS(4 +4)) {
2427 fprintf(stderrstderr, "xhci_port_read: port %d out of bounds\n", port);
2428 return;
2429 }
2430
2431 switch (reg & 0xf) {
2432 case 0x00: /* PORTSC */
2433 portsc = xhci->ports[port].portsc;
2434 /* write-1-to-clear bits*/
2435 portsc &= ~(val & (PORTSC_CSC(1<<17)|PORTSC_PEC(1<<18)|PORTSC_WRC(1<<19)|PORTSC_OCC(1<<20)|
2436 PORTSC_PRC(1<<21)|PORTSC_PLC(1<<22)|PORTSC_CEC(1<<23)));
2437 if (val & PORTSC_LWS(1<<16)) {
2438 /* overwrite PLS only when LWS=1 */
2439 portsc &= ~(PORTSC_PLS_MASK0xf << PORTSC_PLS_SHIFT5);
2440 portsc |= val & (PORTSC_PLS_MASK0xf << PORTSC_PLS_SHIFT5);
2441 }
2442 /* read/write bits */
2443 portsc &= ~(PORTSC_PP(1<<9)|PORTSC_WCE(1<<25)|PORTSC_WDE(1<<26)|PORTSC_WOE(1<<27));
2444 portsc |= (val & (PORTSC_PP(1<<9)|PORTSC_WCE(1<<25)|PORTSC_WDE(1<<26)|PORTSC_WOE(1<<27)));
2445 /* write-1-to-start bits */
2446 if (val & PORTSC_PR(1<<4)) {
2447 DPRINTF("xhci: port %d reset\n", port)do {} while (0);
2448 usb_device_reset(xhci->ports[port].port.dev);
2449 portsc |= PORTSC_PRC(1<<21) | PORTSC_PED(1<<1);
2450 }
2451 xhci->ports[port].portsc = portsc;
2452 break;
2453 case 0x04: /* PORTPMSC */
2454 case 0x08: /* PORTLI */
2455 default:
2456 fprintf(stderrstderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2457 port, reg);
2458 }
2459}
2460
2461static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2462{
2463 uint32_t ret;
2464
2465 if (reg >= 0x400) {
2466 return xhci_port_read(xhci, reg - 0x400);
2467 }
2468
2469 switch (reg) {
2470 case 0x00: /* USBCMD */
2471 ret = xhci->usbcmd;
2472 break;
2473 case 0x04: /* USBSTS */
2474 ret = xhci->usbsts;
2475 break;
2476 case 0x08: /* PAGESIZE */
2477 ret = 1; /* 4KiB */
2478 break;
2479 case 0x14: /* DNCTRL */
2480 ret = xhci->dnctrl;
2481 break;
2482 case 0x18: /* CRCR low */
2483 ret = xhci->crcr_low & ~0xe;
2484 break;
2485 case 0x1c: /* CRCR high */
2486 ret = xhci->crcr_high;
2487 break;
2488 case 0x30: /* DCBAAP low */
2489 ret = xhci->dcbaap_low;
2490 break;
2491 case 0x34: /* DCBAAP high */
2492 ret = xhci->dcbaap_high;
2493 break;
2494 case 0x38: /* CONFIG */
2495 ret = xhci->config;
2496 break;
2497 default:
2498 fprintf(stderrstderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2499 ret = 0;
2500 }
2501
2502 trace_usb_xhci_oper_read(reg, ret);
2503 return ret;
2504}
2505
2506static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2507{
2508 if (reg >= 0x400) {
2509 xhci_port_write(xhci, reg - 0x400, val);
2510 return;
2511 }
2512
2513 trace_usb_xhci_oper_write(reg, val);
2514
2515 switch (reg) {
2516 case 0x00: /* USBCMD */
2517 if ((val & USBCMD_RS(1<<0)) && !(xhci->usbcmd & USBCMD_RS(1<<0))) {
2518 xhci_run(xhci);
2519 } else if (!(val & USBCMD_RS(1<<0)) && (xhci->usbcmd & USBCMD_RS(1<<0))) {
2520 xhci_stop(xhci);
2521 }
2522 xhci->usbcmd = val & 0xc0f;
2523 if (val & USBCMD_HCRST(1<<1)) {
2524 xhci_reset(&xhci->pci_dev.qdev);
2525 }
2526 xhci_irq_update(xhci);
2527 break;
2528
2529 case 0x04: /* USBSTS */
2530 /* these bits are write-1-to-clear */
2531 xhci->usbsts &= ~(val & (USBSTS_HSE(1<<2)|USBSTS_EINT(1<<3)|USBSTS_PCD(1<<4)|USBSTS_SRE(1<<10)));
2532 xhci_irq_update(xhci);
2533 break;
2534
2535 case 0x14: /* DNCTRL */
2536 xhci->dnctrl = val & 0xffff;
2537 break;
2538 case 0x18: /* CRCR low */
2539 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR(1<<3));
2540 break;
2541 case 0x1c: /* CRCR high */
2542 xhci->crcr_high = val;
2543 if (xhci->crcr_low & (CRCR_CA(1<<2)|CRCR_CS(1<<1)) && (xhci->crcr_low & CRCR_CRR(1<<3))) {
2544 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2545 xhci->crcr_low &= ~CRCR_CRR(1<<3);
2546 xhci_event(xhci, &event);
2547 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low)do {} while (0);
2548 } else {
2549 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2550 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2551 }
2552 xhci->crcr_low &= ~(CRCR_CA(1<<2) | CRCR_CS(1<<1));
2553 break;
2554 case 0x30: /* DCBAAP low */
2555 xhci->dcbaap_low = val & 0xffffffc0;
2556 break;
2557 case 0x34: /* DCBAAP high */
2558 xhci->dcbaap_high = val;
2559 break;
2560 case 0x38: /* CONFIG */
2561 xhci->config = val & 0xff;
2562 break;
2563 default:
2564 fprintf(stderrstderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2565 }
2566}
2567
2568static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2569{
2570 uint32_t ret;
2571
2572 switch (reg) {
2573 case 0x00: /* MFINDEX */
2574 fprintf(stderrstderr, "xhci_runtime_read: MFINDEX not yet implemented\n");
2575 ret = xhci->mfindex;
2576 break;
2577 case 0x20: /* IMAN */
2578 ret = xhci->iman;
2579 break;
2580 case 0x24: /* IMOD */
2581 ret = xhci->imod;
2582 break;
2583 case 0x28: /* ERSTSZ */
2584 ret = xhci->erstsz;
2585 break;
2586 case 0x30: /* ERSTBA low */
2587 ret = xhci->erstba_low;
2588 break;
2589 case 0x34: /* ERSTBA high */
2590 ret = xhci->erstba_high;
2591 break;
2592 case 0x38: /* ERDP low */
2593 ret = xhci->erdp_low;
2594 break;
2595 case 0x3c: /* ERDP high */
2596 ret = xhci->erdp_high;
2597 break;
2598 default:
2599 fprintf(stderrstderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2600 ret = 0;
2601 }
2602
2603 trace_usb_xhci_runtime_read(reg, ret);
2604 return ret;
2605}
2606
2607static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2608{
2609 trace_usb_xhci_runtime_read(reg, val);
2610
2611 switch (reg) {
2612 case 0x20: /* IMAN */
2613 if (val & IMAN_IP(1<<0)) {
2614 xhci->iman &= ~IMAN_IP(1<<0);
2615 }
2616 xhci->iman &= ~IMAN_IE(1<<1);
2617 xhci->iman |= val & IMAN_IE(1<<1);
2618 xhci_irq_update(xhci);
2619 break;
2620 case 0x24: /* IMOD */
2621 xhci->imod = val;
2622 break;
2623 case 0x28: /* ERSTSZ */
2624 xhci->erstsz = val & 0xffff;
2625 break;
2626 case 0x30: /* ERSTBA low */
2627 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2628 xhci->erstba_low = val & 0xffffffc0; */
2629 xhci->erstba_low = val & 0xfffffff0;
2630 break;
2631 case 0x34: /* ERSTBA high */
2632 xhci->erstba_high = val;
2633 xhci_er_reset(xhci);
2634 break;
2635 case 0x38: /* ERDP low */
2636 if (val & ERDP_EHB(1<<3)) {
2637 xhci->erdp_low &= ~ERDP_EHB(1<<3);
2638 }
2639 xhci->erdp_low = (val & ~ERDP_EHB(1<<3)) | (xhci->erdp_low & ERDP_EHB(1<<3));
2640 break;
2641 case 0x3c: /* ERDP high */
2642 xhci->erdp_high = val;
2643 xhci_events_update(xhci);
2644 break;
2645 default:
2646 fprintf(stderrstderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2647 }
2648}
2649
2650static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2651{
2652 /* doorbells always read as 0 */
2653 trace_usb_xhci_doorbell_read(reg, 0);
2654 return 0;
2655}
2656
2657static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2658{
2659 trace_usb_xhci_doorbell_write(reg, val);
2660
2661 if (!xhci_running(xhci)) {
2662 fprintf(stderrstderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2663 return;
2664 }
2665
2666 reg >>= 2;
2667
2668 if (reg == 0) {
2669 if (val == 0) {
2670 xhci_process_commands(xhci);
2671 } else {
2672 fprintf(stderrstderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2673 }
2674 } else {
2675 if (reg > MAXSLOTS8) {
2676 fprintf(stderrstderr, "xhci: bad doorbell %d\n", reg);
2677 } else if (val > 31) {
2678 fprintf(stderrstderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2679 } else {
2680 xhci_kick_ep(xhci, reg, val);
2681 }
2682 }
2683}
2684
2685static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2686 unsigned size)
2687{
2688 XHCIState *xhci = ptr;
2689
2690 /* Only aligned reads are allowed on xHCI */
2691 if (addr & 3) {
2692 fprintf(stderrstderr, "xhci_mem_read: Mis-aligned read\n");
2693 return 0;
2694 }
2695
2696 if (addr < LEN_CAP0x40) {
2697 return xhci_cap_read(xhci, addr);
2698 } else if (addr >= OFF_OPER0x40 && addr < (OFF_OPER0x40 + LEN_OPER(0x400 + 0x10 * (4 +4)))) {
2699 return xhci_oper_read(xhci, addr - OFF_OPER0x40);
2700 } else if (addr >= OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) && addr < (OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + LEN_RUNTIME(0x20 + 1 * 0x20))) {
2701 return xhci_runtime_read(xhci, addr - OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f));
2702 } else if (addr >= OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)) && addr < (OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)) + LEN_DOORBELL((8 + 1) * 0x20))) {
2703 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)));
2704 } else {
2705 fprintf(stderrstderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2706 return 0;
2707 }
2708}
2709
2710static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2711 uint64_t val, unsigned size)
2712{
2713 XHCIState *xhci = ptr;
2714
2715 /* Only aligned writes are allowed on xHCI */
2716 if (addr & 3) {
2717 fprintf(stderrstderr, "xhci_mem_write: Mis-aligned write\n");
2718 return;
2719 }
2720
2721 if (addr >= OFF_OPER0x40 && addr < (OFF_OPER0x40 + LEN_OPER(0x400 + 0x10 * (4 +4)))) {
2722 xhci_oper_write(xhci, addr - OFF_OPER0x40, val);
2723 } else if (addr >= OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) && addr < (OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + LEN_RUNTIME(0x20 + 1 * 0x20))) {
2724 xhci_runtime_write(xhci, addr - OFF_RUNTIME((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f), val);
2725 } else if (addr >= OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)) && addr < (OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)) + LEN_DOORBELL((8 + 1) * 0x20))) {
2726 xhci_doorbell_write(xhci, addr - OFF_DOORBELL(((0x40 + (0x400 + 0x10 * (4 +4)) + 0x20) & ~0x1f) + (0x20
+ 1 * 0x20)), val);
2727 } else {
2728 fprintf(stderrstderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2729 }
2730}
2731
2732static const MemoryRegionOps xhci_mem_ops = {
2733 .read = xhci_mem_read,
2734 .write = xhci_mem_write,
2735 .valid.min_access_size = 4,
2736 .valid.max_access_size = 4,
2737 .endianness = DEVICE_LITTLE_ENDIAN,
2738};
2739
2740static void xhci_attach(USBPort *usbport)
2741{
2742 XHCIState *xhci = usbport->opaque;
2743 XHCIPort *port = &xhci->ports[usbport->index];
2744
2745 xhci_update_port(xhci, port, 0);
2746}
2747
2748static void xhci_detach(USBPort *usbport)
2749{
2750 XHCIState *xhci = usbport->opaque;
2751 XHCIPort *port = &xhci->ports[usbport->index];
2752
2753 xhci_update_port(xhci, port, 1);
2754}
2755
2756static void xhci_wakeup(USBPort *usbport)
2757{
2758 XHCIState *xhci = usbport->opaque;
2759 XHCIPort *port = &xhci->ports[usbport->index];
2760 int nr = port->port.index + 1;
2761 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2762 uint32_t pls;
2763
2764 pls = (port->portsc >> PORTSC_PLS_SHIFT5) & PORTSC_PLS_MASK0xf;
2765 if (pls != 3) {
2766 return;
2767 }
2768 port->portsc |= 0xf << PORTSC_PLS_SHIFT5;
2769 if (port->portsc & PORTSC_PLC(1<<22)) {
2770 return;
2771 }
2772 port->portsc |= PORTSC_PLC(1<<22);
2773 xhci_event(xhci, &ev);
2774}
2775
2776static void xhci_complete(USBPort *port, USBPacket *packet)
2777{
2778 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet)({ const typeof(((XHCITransfer *) 0)->packet) *__mptr = (packet
); (XHCITransfer *) ((char *) __mptr - __builtin_offsetof(XHCITransfer
, packet));});
2779
2780 xhci_complete_packet(xfer, packet->result);
2781 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2782}
2783
2784static void xhci_child_detach(USBPort *port, USBDevice *child)
2785{
2786 FIXME()do { fprintf(stderr, "FIXME %s:%d\n", __func__, 2786); abort(
); } while (0);
2787}
2788
2789static USBPortOps xhci_port_ops = {
2790 .attach = xhci_attach,
2791 .detach = xhci_detach,
2792 .wakeup = xhci_wakeup,
2793 .complete = xhci_complete,
2794 .child_detach = xhci_child_detach,
2795};
2796
2797static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev)
2798{
2799 XHCISlot *slot;
2800 int slotid;
2801
2802 for (slotid = 1; slotid <= MAXSLOTS8; slotid++) {
2803 slot = &xhci->slots[slotid-1];
2804 if (slot->devaddr == dev->addr) {
2805 return slotid;
2806 }
2807 }
2808 return 0;
2809}
2810
2811static int xhci_find_epid(USBEndpoint *ep)
2812{
2813 if (ep->nr == 0) {
2814 return 1;
2815 }
2816 if (ep->pid == USB_TOKEN_IN0x69) {
2817 return ep->nr * 2 + 1;
2818 } else {
2819 return ep->nr * 2;
2820 }
2821}
2822
2823static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
2824{
2825 XHCIState *xhci = container_of(bus, XHCIState, bus)({ const typeof(((XHCIState *) 0)->bus) *__mptr = (bus); (
XHCIState *) ((char *) __mptr - __builtin_offsetof(XHCIState,
bus));});
2826 int slotid;
2827
2828 DPRINTF("%s\n", __func__)do {} while (0);
2829 slotid = xhci_find_slotid(xhci, ep->dev);
2830 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
2831 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr)do {} while (0);
2832 return;
2833 }
2834 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep));
2835}
2836
2837static USBBusOps xhci_bus_ops = {
2838 .wakeup_endpoint = xhci_wakeup_endpoint,
2839};
2840
2841static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2842{
2843 int i;
2844
2845 xhci->usbsts = USBSTS_HCH(1<<0);
2846
2847 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2848
2849 for (i = 0; i < MAXPORTS(4 +4); i++) {
2850 memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
2851 usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
2852 &xhci_port_ops,
2853 USB_SPEED_MASK_LOW(1 << 0) |
2854 USB_SPEED_MASK_FULL(1 << 1) |
2855 USB_SPEED_MASK_HIGH(1 << 2));
2856 }
2857 for (i = 0; i < MAXSLOTS8; i++) {
2858 xhci->slots[i].enabled = 0;
2859 }
2860}
2861
2862static int usb_xhci_initfn(struct PCIDevice *dev)
2863{
2864 int ret;
2865
2866 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(XHCIState, pci_dev)]; ({ const typeof((
(XHCIState *) 0)->pci_dev) *__mptr = (dev); (XHCIState *) (
(char *) __mptr - __builtin_offsetof(XHCIState, pci_dev));});
}));
2867
2868 xhci->pci_dev.config[PCI_CLASS_PROG0x09] = 0x30; /* xHCI */
2869 xhci->pci_dev.config[PCI_INTERRUPT_PIN0x3d] = 0x01; /* interrupt pin 1 */
2870 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE0x0c] = 0x10;
2871 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2872
2873 usb_xhci_init(xhci, &dev->qdev);
2874
2875 xhci->irq = xhci->pci_dev.irq[0];
2876
2877 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2878 "xhci", LEN_REGS0x2000);
2879 pci_register_bar(&xhci->pci_dev, 0,
2880 PCI_BASE_ADDRESS_SPACE_MEMORY0x00|PCI_BASE_ADDRESS_MEM_TYPE_640x04,
2881 &xhci->mem);
2882
2883 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT0x0, 0);
2884 assert(ret >= 0)((ret >= 0) ? (void) (0) : __assert_fail ("ret >= 0", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2884, __PRETTY_FUNCTION__));
2885
2886 if (xhci->msi) {
2887 ret = msi_init(&xhci->pci_dev, 0x70, 1, true1, false0);
2888 assert(ret >= 0)((ret >= 0) ? (void) (0) : __assert_fail ("ret >= 0", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2888, __PRETTY_FUNCTION__));
2889 }
2890
2891 return 0;
2892}
2893
2894static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
2895 int len)
2896{
2897 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(XHCIState, pci_dev)]; ({ const typeof((
(XHCIState *) 0)->pci_dev) *__mptr = (dev); (XHCIState *) (
(char *) __mptr - __builtin_offsetof(XHCIState, pci_dev));});
}));
2898
2899 pci_default_write_config(dev, addr, val, len);
2900 if (xhci->msi) {
2901 msi_write_config(dev, addr, val, len);
2902 }
2903}
2904
2905static const VMStateDescription vmstate_xhci = {
2906 .name = "xhci",
2907 .unmigratable = 1,
2908};
2909
2910static Property xhci_properties[] = {
2911 DEFINE_PROP_UINT32("msi", XHCIState, msi, 0){ .name = ("msi"), .info = &(qdev_prop_uint32), .offset =
__builtin_offsetof(XHCIState, msi) + ((uint32_t*)0 - (typeof
(((XHCIState *)0)->msi)*)0), .qtype = QTYPE_QINT, .defval =
(uint32_t)0, },
2912 DEFINE_PROP_END_OF_LIST(){},
2913};
2914
2915static void xhci_class_init(ObjectClass *klass, void *data)
2916{
2917 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device")));
2918 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device")));
2919
2920 dc->vmsd = &vmstate_xhci;
2921 dc->props = xhci_properties;
2922 dc->reset = xhci_reset;
2923 k->init = usb_xhci_initfn;
2924 k->vendor_id = PCI_VENDOR_ID_NEC0x1033;
2925 k->device_id = PCI_DEVICE_ID_NEC_UPD7202000x0194;
2926 k->class_id = PCI_CLASS_SERIAL_USB0x0c03;
2927 k->revision = 0x03;
2928 k->is_express = 1;
2929 k->config_write = xhci_write_config;
2930}
2931
2932static TypeInfo xhci_info = {
2933 .name = "nec-usb-xhci",
2934 .parent = TYPE_PCI_DEVICE"pci-device",
2935 .instance_size = sizeof(XHCIState),
2936 .class_init = xhci_class_init,
2937};
2938
2939static void xhci_register_types(void)
2940{
2941 type_register_static(&xhci_info);
2942}
2943
2944type_init(xhci_register_types)static void __attribute__((constructor)) do_qemu_init_xhci_register_types
(void) { register_module_init(xhci_register_types, MODULE_INIT_QOM
); }